{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570GT100I5","brand":"Intel","brandSlug":"intel","productSlug":"EPM570GT100I5","canonicalUrl":"https://icboms.com/intel/EPM570GT100I5","factsUrl":"https://icboms.com/api/mcp/products/EPM570GT100I5","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM570GT100I5, 440 macrocells, 570 logic elements, 76 I/O, 5.4 ns tpd, 100-TQFP (14x14), 1.8 V core, -40°C to 100°C, tray.","salesMarkdown":"## Active production, 440 macrocells, 5.4 ns pin-to-pin The EPM570GT100I5: The 5.4 ns propagation delay (tpd1 max) is the pin-to-pin combinatorial delay at the worst-case corner — it governs the clock-to-output path and the setup margin for any registered input. ## I/O budget and supply rails 76 user I/O pins are available in the 100-TQFP package. The core runs from 1.71 V to 1.89 V (1.8 V nominal) — a single 1.8 V rail powers the logic array and the in-system programming controller. The I/O banks operate at the same 1.8 V level, so level translation is needed when interfacing to 3.3 V peripherals. ## Sourcing and supply posture The MAX II family uses a 1.8 V flash-based fabric that retains the configuration on power-off — no external configuration memory or boot-up delay. The in-system programmable (ISP) interface supports JTAG programming via a standard 10-pin header, and the 440 macrocells are sufficient for address decoding, state machines, and bus arbitration in a typical industrial control card.","metaTitle":"Intel EPM570GT100I5 MAX II CPLD, 440 macrocells, 5.4 ns","metaDescription":"Intel EPM570GT100I5 MAX II CPLD, active production, 440 macrocells, 5.4 ns tpd, 76 I/O, 100-TQFP, -40°C to 100°C. Sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"76","Package / Case":"100-TQFP","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"-40°C~100°C(TJ)","Supplier Device Package":"100-TQFP (14x14)","Voltage Supply - Internal":"1.71V ~ 1.89V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$7.8800","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"Where can I buy the EPM570GT100I5 and what is the price?","answer":"Submit an RFQ to confirm current availability and pricing — stock levels and per-unit cost are quoted at the time of request, not listed here."},{"question":"What is the difference between the EPM570GT100I5 and the EPM570GT100C5?","answer":"The difference is the temperature grade. The logic fabric, macrocells, I/O count, and package are identical."},{"question":"How do I program the EPM570GT100I5?","answer":"The EPM570GT100I5 is in-system programmable via a standard JTAG interface (IEEE 1149.1). Intel's Quartus Prime software generates the programming file and drives the chain through a USB-Blaster or similar JTAG download cable. The flash-based fabric retains the configuration on power-off."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570GT100I5","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570GT100I5 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}