{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570GT100C5","brand":"Intel","brandSlug":"intel","productSlug":"EPM570GT100C5","canonicalUrl":"https://icboms.com/intel/EPM570GT100C5","factsUrl":"https://icboms.com/api/mcp/products/EPM570GT100C5","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II series CPLD, EPM570GT100C5, 570 logic elements, 440 macrocells, 5.4 ns pin-to-pin delay, 76 I/O, 100-TQFP (14x14 mm), 1.71V–1.89V core, 0°C to 85°C, in-system programmable.","salesMarkdown":"## MAX II CPLD — 570 LEs, 5.4 ns, 76 I/O The Intel EPM570GT100C5 is a MAX® II family CPLD delivering 570 logic elements and 440 macrocells in a 100-TQFP (14x14 mm) package. Pin-to-pin propagation delay (tpd1) maxes at 5.4 ns, making it a fit for address decoding, bus bridging, and state-machine glue logic where combinatorial speed matters. The 76 user I/O give enough headroom for a moderate-density interface without stepping up to a larger package. Core supply is 1.71 V to 1.89 V, with in-system programmability via JTAG — no external programmer voltage needed. Operating temperature covers 0°C to 85°C, suited for commercial and industrial indoor environments.","metaTitle":"Intel EPM570GT100C5 CPLD, MAX II, 570 LE, 5.4 ns","metaDescription":"Intel EPM570GT100C5 MAX II CPLD: 570 logic elements, 440 macrocells, 5.4 ns tpd, 76 I/O in 100-TQFP. Active lifecycle, sourced to order. Request a quote.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"76","Package / Case":"100-TQFP","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"0°C~85°C(TJ)","Supplier Device Package":"100-TQFP (14x14)","Voltage Supply - Internal":"1.71V ~ 1.89V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$69.0000","priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/EPM570GT100C5/alternatives.json"},"ai":{"faq":[{"question":"What is the difference between EPM570GT100C5 and EPM570T100C5?","answer":"The 'G' in EPM570GT100C5 indicates a specific ordering code variant within the MAX II family — typically a lead-free or RoHS-compliant finish. The EPM570T100C5 is a non-'G' variant; the core logic (570 LEs, 440 macrocells, 5.4 ns) is identical. Confirm the exact finish requirement with your BOM before substituting."},{"question":"Where can I buy EPM570GT100C5?","answer":"This part is sourced and quoted to order through independent distribution. Submit an RFQ for current pricing and availability — lead time and stock position are confirmed at quote time."},{"question":"How to program the Intel EPM570GT100C5?","answer":"The EPM570GT100C5 is in-system programmable via the JTAG interface (IEEE 1149.1). Intel's Quartus II software (or later) generates the programming file; a standard USB-Blaster or compatible JTAG cable connects to the TMS, TCK, TDI, TDO pins. No external VPP supply is needed — the core voltage supplies the programming logic."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570GT100C5","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570GT100C5 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}