{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570GF256C4N","brand":"Intel","brandSlug":"intel","productSlug":"EPM570GF256C4N","canonicalUrl":"https://icboms.com/intel/EPM570GF256C4N","factsUrl":"https://icboms.com/api/mcp/products/EPM570GF256C4N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM570GF256C4N, 440 macrocells, 570 logic elements, 5.4 ns tpd, 160 I/O, 256-FBGA (17x17), 1.71V-1.89V, 0°C~85°C, Tray.","salesMarkdown":"## Logic density and propagation delay — the fit decision The EPM570GF256C4N is a MAX® II family CPLD from Intel, packing 440 macrocells and 570 logic elements into a 256-ball FBGA footprint (17x17 mm). The 5.4 ns maximum propagation delay (tpd1) sets the combinational logic ceiling — any path through the CPLD must stay under this budget for the clock period, or the design needs pipelining or a faster part. The 160 user I/O break out to the BGA balls; the 0.8 mm pitch on the 17x17 array demands a 4-layer PCB for fan-out on the inner rows. Core supply is 1.71 V to 1.89 V — a 1.8 V rail with ±5 % tolerance keeps the CPLD inside the operating window. The commercial temperature grade (0 °C to 85 °C junction) covers most indoor and telecom enclosure environments, but not extended industrial or automotive. Decoupling should follow the MAX II hardware checklist: one 0.1 µF ceramic per VCC pair, plus a 10 µF bulk cap per supply plane. ## In-system programming and JTAG support The device is In System Programmable (ISP) via the JTAG interface — the 4-pin TCK/TMS/TDI/TDO chain connects directly to a standard 10-pin JTAG header. No external programming voltage is needed; the core supply powers the programming logic. The MAX II family supports real-time ISP without a dedicated configuration device, so the same JTAG chain can program the CPLD and any downstream FPGA in the same scan path.","metaTitle":"Intel EPM570GF256C4N MAX II CPLD, 440 macrocells, 5.4 ns","metaDescription":"Intel EPM570GF256C4N MAX II CPLD, 440 macrocells, 5.4 ns tpd, 160 I/O, 256-FBGA. Active production, RoHS compliant, JTAG ISP. Sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"160","Package / Case":"256-BGA","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"0°C~85°C(TJ)","Supplier Device Package":"256-FBGA (17x17)","Voltage Supply - Internal":"1.71V ~ 1.89V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$69.0000","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"Is EPM570GF256C4N RoHS compliant?","answer":"Yes, the EPM570GF256C4N is RoHS compliant. The part ships in a Tray package and carries the standard Intel RoHS-compliant marking. No exemption or non-compliant variant is listed for this order code."},{"question":"Does EPM570GF256C4N support JTAG in-system programming?","answer":"Yes, the EPM570GF256C4N is In System Programmable via the JTAG interface. The 4-wire JTAG port (TCK, TMS, TDI, TDO) is powered from the 1.8 V core supply — no separate programming voltage is required. The MAX II family supports concurrent programming of multiple devices in the same JTAG chain."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570GF256C4N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570GF256C4N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}