{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570GF100I5N","brand":"Intel","brandSlug":"intel","productSlug":"EPM570GF100I5N","canonicalUrl":"https://icboms.com/intel/EPM570GF100I5N","factsUrl":"https://icboms.com/api/mcp/products/EPM570GF100I5N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM570GF100I5N, 440 macrocells, 570 logic elements, 76 I/O, 5.4 ns tpd, 1.8 V core, -40 to 100°C, 100-FBGA.","salesMarkdown":"## 440 macrocells, 5.4 ns pin-to-pin — the MAX II sweet spot The Intel EPM570GF100I5N is a MAX® II family CPLD packing 440 macrocells and 570 logic elements in a 100-ball FBGA (11x11 mm). The 5.4 ns propagation delay (tpd1 max) means glue logic, address decoding, or state-machine control fits within a single clock cycle at common bus speeds — no pipeline stages needed for 100 MHz+ interfaces. 76 user I/O in the 100-LBGA package gives enough headroom for a 16-bit data bus plus control signals, with spare pins for board-level test access or a JTAG chain. The 1.71 V to 1.89 V core supply keeps dynamic power low — a consideration when the CPLD sits on a 1.8 V rail shared with an FPGA or processor. ## In-system programmable — no socket, no UV eraser In-system programmability (ISP) via JTAG means the EPM570GF100I5N can be populated, reflowed, and programmed on the board — no separate programming socket or UV eraser needed. This simplifies prototype spins and field updates: the same BOM position accepts multiple logic revisions without a hardware change.","metaTitle":"Intel EPM570GF100I5N MAX II CPLD, 440 macrocells, 5.4 ns","metaDescription":"Intel EPM570GF100I5N MAX II CPLD, 440 macrocells, 5.4 ns tpd, 76 I/O, -40 to 100°C, 100-FBGA. Active production, sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"76","Package / Case":"100-LBGA","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"-40°C~100°C(TJ)","Supplier Device Package":"100-FBGA (11x11)","Voltage Supply - Internal":"1.71V ~ 1.89V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$69.0000","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What is the difference between EPM570GF100I5N and the MAX 7000 peers like EPM7128BFC256-7?","answer":"The EPM570GF100I5N is a MAX II device with 440 macrocells, 570 logic elements, a 1.8 V core, and 5.4 ns tpd — roughly 3.5x the logic density and a lower-voltage, lower-power architecture. They are not pin-compatible; a board spin is required to migrate."},{"question":"Is EPM570GF100I5N RoHS compliant?","answer":"The part number suffix 'N' indicates a lead-free, RoHS-compliant finish per Intel's MAX II marking convention."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570GF100I5N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570GF100I5N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}