{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570F256C3N","brand":"Intel","brandSlug":"intel","productSlug":"EPM570F256C3N","canonicalUrl":"https://icboms.com/intel/EPM570F256C3N","factsUrl":"https://icboms.com/api/mcp/products/EPM570F256C3N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM570F256C3N, 440 macrocells, 570 logic elements, 160 I/O, 5.4 ns tpd, 2.5V/3.3V, 256-FBGA (17x17), 0°C to 85°C.","salesMarkdown":"The Intel EPM570F256C3N is a MAX® II complex programmable logic device (CPLD) built on a look-up-table (LUT) architecture with 570 logic elements and 440 macrocells. It is in-system programmable via JTAG, so no external programmer is needed for board-level updates. The 256-ball FBGA (17x17 mm) package brings 160 user I/O to the board — enough for glue-logic consolidation, address decoding, or bus bridging in a mid-density design. ## 5.4 ns propagation delay — timing closure in context The C3N speed grade specifies a pin-to-pin combinational delay (tpd) of 5.4 ns maximum. ## What the 160 I/O and 256-BGA mean for the board The 256-ball FBGA (17x17 mm) with 160 user I/O is a fine-pitch BGA — expect at least four PCB layers for fanout, with microvias or blind vias if routing density is high. Plan for a JTAG header (TCK, TMS, TDI, TDO) on the board for in-system programming; no external flash is needed because the MAX II configuration is stored in on-chip flash.","metaTitle":"Intel EPM570F256C3N MAX II CPLD, 440 Macrocells, 5.4 ns","metaDescription":"Intel EPM570F256C3N MAX II CPLD: 440 macrocells, 570 logic elements, 160 I/O, 5.4 ns tpd, 256-FBGA. Active production. Sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"160","Package / Case":"256-BGA","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"0°C~85°C(TJ)","Supplier Device Package":"256-FBGA (17x17)","Voltage Supply - Internal":"2.5V, 3.3V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$69.0000","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What are the differences between EPM570F256C3N and other speed grades like C4N or C5N?","answer":"The C3N speed grade specifies a maximum pin-to-pin delay (tpd) of 5.4 ns. Higher-numbered speed grades (C4N, C5N) have slower tpd values — for example, the C5N grade is typically 7.5 ns. The C3N is the fastest standard speed grade in the MAX II family for this density."},{"question":"Is EPM570F256C3N drop-in compatible with EPM570F256C4N?","answer":"Yes, the EPM570F256C3N and EPM570F256C4N share the same base product number (EPM570), same package (256-FBGA), and same pinout — they differ only in speed grade. The C3N is faster (5.4 ns tpd) than the C4N."},{"question":"What are the programming requirements for EPM570F256C3N?","answer":"The EPM570F256C3N is in-system programmable via a standard JTAG interface (TCK, TMS, TDI, TDO). No external programmer or configuration memory is required; the device stores its configuration in on-chip flash."},{"question":"What is EPM570F256C3N's listed series?","answer":"The EPM570F256C3N belongs to the MAX® II series of CPLDs from Intel."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570F256C3N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570F256C3N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}