{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570F100C5N","brand":"Intel","brandSlug":"intel","productSlug":"EPM570F100C5N","canonicalUrl":"https://icboms.com/intel/EPM570F100C5N","factsUrl":"https://icboms.com/api/mcp/products/EPM570F100C5N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM570F100C5N, 440 macrocells, 570 logic elements, 5.4 ns tpd, 76 I/O, 100-FBGA, 2.5V/3.3V, tray.","salesMarkdown":"## Logic density and timing for glue-logic consolidation The Intel EPM570F100C5N is a MAX® II CPLD with 570 logic elements and 440 macrocells, offering a 5.4 ns maximum propagation delay (tpd1) — fast enough to absorb combinatorial decode, address mapping, and state-machine logic that would otherwise consume board space with discrete 74-series parts. ## I/O and package — 76 channels in an 11x11 mm footprint Packaged in a 100-LBGA (11x11 mm FBGA), the device brings out 76 user I/O — enough to interface with a parallel bus, a handful of chip selects, and a few status/control lines without needing a larger package. The 0.8 mm ball pitch is routable on a standard 4-layer PCB with via-in-pad if the design is dense. The commercial temperature range (0°C to 85°C case) covers most indoor and telecom equipment; for extended-temperature environments, check the C4N or C6N speed grades in the same package. ## In-system programmability and JTAG integration The device is in-system programmable via JTAG, so the CPLD can be programmed after the board is assembled — no socket, no pre-programmed parts. The JTAG chain can include other devices on the same 4-wire bus; the CPLD's boundary-scan register also aids board-level test coverage.","metaTitle":"Intel EPM570F100C5N MAX II CPLD, 440 macrocells, 5.4 ns","metaDescription":"Intel EPM570F100C5N MAX II CPLD, 440 macrocells, 5.4 ns tpd, 76 I/O, 100-FBGA. Active production, in-system programmable. Sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Series":"MAX® II","Packaging":"Tray","Part Status":"Active","Manufacturer":"Intel","Mounting Type":"Surface Mount","Number of I/O":"76","Package / Case":"100-LBGA","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"0°C ~ 85°C (TJ)","Supplier Device Package":"100-FBGA (11x11)","Voltage Supply - Internal":"2.5V, 3.3V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$30.3400","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"Where can I buy EPM570F100C5N?","answer":"The EPM570F100C5N is available to order through independent distribution."},{"question":"Can EPM570F100C5N be programmed with JTAG?","answer":"Yes — the device is in-system programmable through its JTAG interface. The JTAG chain can include other devices on the same 4-wire bus, and the CPLD's boundary-scan register supports board-level test coverage."},{"question":"What is the difference between EPM570 and EPM570F?","answer":"The 'F' in EPM570F100C5N denotes the FineLine BGA package (FBGA) — a thinner, smaller-footprint variant of the standard BGA. The '570' logic core (570 logic elements, 440 macrocells) is identical across package options; the difference is the physical package and ball pitch."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570F100C5N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570F100C5N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}