{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM1270T144C3","brand":"Intel","brandSlug":"intel","productSlug":"EPM1270T144C3","canonicalUrl":"https://icboms.com/intel/EPM1270T144C3","factsUrl":"https://icboms.com/api/mcp/products/EPM1270T144C3","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX II CPLD, EPM1270T144C3, 980 macrocells, 1270 logic elements, 116 I/O, 6.2 ns tpd(1) max, 2.5V/3.3V internal supply, 0°C to 85°C, 144-LQFP tray.","salesMarkdown":"## Active production — no phase-out risk for current BOMs The EPM1270T144C3: That means it remains a safe commitment for production builds — no last-time-buy deadline to hedge, no forced migration path to budget for. For a procurement desk evaluating single-source risk, this part is still in the official supply channel. ## Density and speed — where the 1270 LEs land in a real board With 1270 logic elements and 980 macrocells, the EPM1270T144C3 sits near the top of the MAX II family — enough density to absorb a handful of 74-series glue-logic ICs, a small address decoder, a state machine, and some I/O expansion into a single 144-pin package. The 116 I/O pins give headroom for a 32-bit bus plus control signals without multiplexing. The 6.2 ns tpd(1) max delay sets the combinatorial propagation ceiling. That means a signal entering a macrocell through a registered path and exiting through a combinatorial output takes at most 6.2 ns from pin to pin. For a 50 MHz system clock (20 ns period), that leaves about 14 ns for routing, setup, and clock skew — workable for most glue-logic paths, but tight for wide fan-in combinatorial functions that cascade through multiple LEs. ## Supply rails and temperature grade — the board-level constraints The part is not single-rail; both voltages must be present on the board. The 0°C to 85°C commercial temperature range limits deployment to indoor, conditioned environments — no industrial or automotive exposure without active thermal management. ## Package and programming — what the assembly line needs to know The tray packaging means the feeder section needs a tray handler or a tube adapter; the parts do not come on tape-and-reel. In-system programmable via the JTAG interface, so a board-level firmware update does not require removing the device or using a socket adapter. The MAX II family programs with Quartus II software (version 9.1 or later) — no external programmer needed for the JTAG chain.","metaTitle":"Intel EPM1270T144C3 CPLD, MAX II, 980 macrocells, 6.2 ns","metaDescription":"Intel MAX II CPLD EPM1270T144C3: 1270 LEs, 980 macrocells, 116 I/O, 6.2 ns tpd, 2.5V/3.3V, 0-85C, 144-LQFP tray. Active production — sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"116","Package / Case":"144-LQFP","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM1270","Number of Macrocells":"980","Delay Time tpd(1) Max":"6.2 ns","Operating Temperature":"0°C~85°C(TJ)","Supplier Device Package":"144-TQFP (20x20)","Voltage Supply - Internal":"2.5V, 3.3V","Number of Logic Elements/Blocks":"1270"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$156.0000","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What is the difference between the EPM1270T144C3 and the EPM1270T144C4?","answer":"The suffix C3 vs C4 indicates the speed grade. The C3 variant has a 6.2 ns tpd(1) max delay, while the C4 variant is slower at 7.5 ns. All other parametrics — 1270 LEs, 980 macrocells, 116 I/O, 2.5V/3.3V supply, 144-LQFP package — are identical between the two. For timing-critical paths, the C3 is the faster pick."},{"question":"Can the EPM1270T144C3 be programmed with Quartus?","answer":"Yes — the MAX II family is supported by Intel Quartus II software (version 9.1 or later). Programming is done through the JTAG interface, and the device is in-system programmable, so no external programmer is required for board-level reflash."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM1270T144C3","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM1270T144C3 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}