{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM1270GT144I5N","brand":"Intel","brandSlug":"intel","productSlug":"EPM1270GT144I5N","canonicalUrl":"https://icboms.com/intel/EPM1270GT144I5N","factsUrl":"https://icboms.com/api/mcp/products/EPM1270GT144I5N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX II CPLD, EPM1270GT144I5N, 1270 logic elements, 980 macrocells, 6.2 ns tpd, 116 I/O, 1.71 V–1.89 V core, -40°C to 100°C, 144-TQFP.","salesMarkdown":"## Sourcing and lifecycle reality Intel lists the EPM1270GT144I5N as Active, but the MAX II family is mature. No official last-time-buy notice is posted. ## What the 6.2 ns delay means for your bus The 6.2 ns pin-to-pin delay (tpd) is the worst-case combinatorial path through one macrocell.","metaTitle":"Intel MAX II CPLD EPM1270GT144I5N, 980 macrocells, 6.2 ns, -40°C to 100°C","metaDescription":"Intel MAX II CPLD EPM1270GT144I5N — 1270 logic elements, 980 macrocells, 6.2 ns pin-to-pin delay, 116 I/O, 144-TQFP, -40°C to 100°C. Sourced to order; request a quote.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"116","Package / Case":"144-LQFP","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM1270","Number of Macrocells":"980","Delay Time tpd(1) Max":"6.2 ns","Operating Temperature":"-40°C~100°C(TJ)","Supplier Device Package":"144-TQFP (20x20)","Voltage Supply - Internal":"1.71V ~ 1.89V","Number of Logic Elements/Blocks":"1270"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$69.0000","priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/EPM1270GT144I5N/alternatives.json"},"ai":{"faq":[{"question":"Is EPM1270GT144I5N obsolete?","answer":"Intel lists the EPM1270GT144I5N as Active as of the latest data. No formal discontinuation notice has been issued, but the MAX II family is mature. For long-term BOM security, plan for a future migration."},{"question":"What is the operating temperature range of EPM1270GT144I5N?","answer":"The EPM1270GT144I5N is rated for -40°C to 100°C junction temperature, making it suitable for industrial and outdoor environments."},{"question":"What is the difference between EPM1270GT144I5N and EPM1270GT144C5N?","answer":"The I5N suffix indicates the industrial temperature range (-40°C to 100°C), while the C5N variant is commercial grade (0°C to 85°C). All other specs — logic density, I/O count, package — are identical."},{"question":"What is the pinout of EPM1270GT144I5N?","answer":"The pinout is standard for the 144-TQFP MAX II CPLD. Refer to the Intel MAX II datasheet for the complete pin assignment table — the 116 user I/O are arranged around the four sides of the package."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM1270GT144I5N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM1270GT144I5N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}