{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM1270F256C5N","brand":"Intel","brandSlug":"intel","productSlug":"EPM1270F256C5N","canonicalUrl":"https://icboms.com/intel/EPM1270F256C5N","factsUrl":"https://icboms.com/api/mcp/products/EPM1270F256C5N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM1270F256C5N, 980 macrocells, 212 I/O, 6.2 ns tpd1, 256-FBGA (17x17 mm), 2.5V/3.3V, 0°C~85°C, Tray.","salesMarkdown":"## 980 macrocells, 6.2 ns — mid-density CPLD for glue-logic consolidation The Intel EPM1270F256C5N is a MAX II family CPLD with 980 macrocells and 1270 logic elements — enough to absorb multiple 74-series logic functions, address decoders, and state machines into a single programmable device. Pin-to-pin propagation delay (tpd1) is 6.2 ns max, which sets the ceiling for combinatorial path speed — fast enough for most bus-interface and control applications running at 100+ MHz. ## Active production — no obsolescence risk on this BOM line For a procurement review, this means the part is a safe drop-in for current builds without a last-time-buy deadline. ## Dual-voltage supply and commercial temperature range Core runs at 2.5 V while the I/O banks operate at 3.3 V — a common split that lets the CPLD interface directly with 3.3 V peripherals without external level shifters. The 256-FBGA (17x17 mm) footprint requires a multi-layer PCB for fan-out — the 0.8 mm ball pitch is manageable with standard 4-layer stack-ups. ## In-system programmable via JTAG — no socket needed The device is in-system programmable through the JTAG interface, so firmware updates and field reconfigurations do not require a separate programmer or removal from the board.","metaTitle":"Intel EPM1270F256C5N MAX II CPLD, 980 macrocells, 6.2 ns","metaDescription":"Intel MAX II CPLD, 980 macrocells, 212 I/O, 6.2 ns tpd1, 256-FBGA. Active production. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"212","Package / Case":"256-BGA","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM1270","Number of Macrocells":"980","Delay Time tpd(1) Max":"6.2 ns","Operating Temperature":"0°C~85°C(TJ)","Supplier Device Package":"256-FBGA (17x17)","Voltage Supply - Internal":"2.5V, 3.3V","Number of Logic Elements/Blocks":"1270"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$54.6000","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What is the difference between EPM1270F256C5N and EPM1270F256C4N?","answer":"The suffix denotes the speed grade — the C5N variant has a 6.2 ns tpd1 max, while the C4N is a faster grade (lower tpd1). Both share the same macrocell count, I/O, and package."},{"question":"Can EPM1270F256C5N be programmed with JTAG?","answer":"Yes — the EPM1270F256C5N is in-system programmable via the JTAG interface, supporting both initial programming and field updates without a separate programmer."},{"question":"Is EPM1270F256C5N RoHS compliant?","answer":"The part number suffix 'C5N' indicates a RoHS-compliant, lead-free finish per Intel's standard CPLD ordering code."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM1270F256C5N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM1270F256C5N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}