{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM1270F256C3N","brand":"Intel","brandSlug":"intel","productSlug":"EPM1270F256C3N","canonicalUrl":"https://icboms.com/intel/EPM1270F256C3N","factsUrl":"https://icboms.com/api/mcp/products/EPM1270F256C3N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM1270F256C3N, 1270 logic elements, 980 macrocells, 6.2 ns tpd, 212 I/O, 256-FBGA (17x17), 2.5V/3.3V, 0°C to 85°C, Tray.","salesMarkdown":"## Logic capacity and timing margin The EPM1270F256C3N belongs to the MAX® II family, Intel's low-power instant-on CPLD architecture. It integrates 1270 logic elements configured as 980 macrocells, giving it the density for medium-scale glue logic, address decoding, or peripheral control without the configuration latency of an FPGA. Maximum propagation delay tpd(1) is 6.2 ns, which sets the combinatorial path ceiling from any input to any output. For a 50 MHz bus interface, this leaves roughly 14 ns of cycle time after tpd — enough margin for setup and hold at the downstream register, but a 100 MHz interface would require pipelining or a faster CPLD. ## I/O count and BGA footprint 212 user I/O pins route through a 256-ball FBGA package measuring 17x17 mm. ## Supply rails and in-system programming The core logic runs at the lower rail to cut dynamic power; the I/O banks can operate at either voltage depending on the interface standard. In-system programmable via JTAG — no external programmer voltage is needed, and the non-volatile configuration holds through power cycles without a configuration PROM. This is the commercial-industrial overlap band — suitable for telecom equipment in a climate-controlled shelter, factory-floor controllers with forced air, or outdoor enclosures that stay above freezing. Not qualified for the -40°C cold crank or 125°C under-hood environment; those would require the industrial-grade suffix variant. Intel lists the EPM1270F256C3N as Active.","metaTitle":"Intel EPM1270F256C3N MAX II CPLD, 980 macrocells, 6.2 ns","metaDescription":"Intel MAX II CPLD, 980 macrocells, 6.2 ns tpd, 212 I/O, 256-FBGA. Active production. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"212","Package / Case":"256-BGA","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM1270","Number of Macrocells":"980","Delay Time tpd(1) Max":"6.2 ns","Operating Temperature":"0°C~85°C(TJ)","Supplier Device Package":"256-FBGA (17x17)","Voltage Supply - Internal":"2.5V, 3.3V","Number of Logic Elements/Blocks":"1270"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$12.0600","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What is the closest pin-compatible alternative to EPM1270F256C3N?","answer":"Within the MAX II family, the EPM1270F256C5N is the same 256-FBGA package and same logic density but with a faster 5.0 ns tpd speed grade. The C3N is the commercial-temperature, slower-speed variant."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM1270F256C3N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM1270F256C3N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}