{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY8C5867LTI-LP025","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY8C5867LTI-LP025","canonicalUrl":"https://icboms.com/infineon/CY8C5867LTI-LP025","factsUrl":"https://icboms.com/api/mcp/products/CY8C5867LTI-LP025","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies PSoC® 5 CY8C58LP ARM Cortex-M3 MCU, CY8C5867LTI-LP025, 67 MHz, 128 KB FLASH, 32K x 8 RAM, 2K x 8 EEPROM, 38 I/O, 68-VFQFN Exposed Pad, Tray.","salesMarkdown":"The CY8C5867LTI-LP025: This is a design-in viable part, not a shortage-era scavenge. The PSoC 5 toolchain and SDK are mature; the part ships in tray packaging and the 68-QFN footprint is standard across the CY8C58LP family. ## 67 MHz Cortex-M3 with 128 KB flash — memory budget check The ARM Cortex-M3 core runs at 67 MHz — enough for a capacitive-touch HMI polling at 100 Hz while the DMA engine moves ADC results into SRAM without CPU intervention. The 128 KB flash holds the application binary plus a bootloader; the 32 KB SRAM leaves roughly 12-16 KB for the stack and heap after the HAL and a small RTOS footprint. The 2 KB EEPROM stores calibration constants and failsafe parameters without wearing the flash sectors. ## 20-bit ADC and CapSense — analog front-end for sensor fusion The data converter block includes a 20-bit delta-sigma ADC and a separate 12-bit SAR ADC — the 20-bit channel handles precision strain-gauge or thermocouple inputs, while the 12-bit SAR scans multiple analog channels at higher throughput. Four 8-bit DACs provide analog set-points or waveform generation. The CapSense peripheral implements self- and mutual-capacitance touch sensing without an external touch controller; the DMA engine streams the raw counts to SRAM for post-processing. The 38 general-purpose I/O include the CapSense shield electrode and the LCD segment drive — the LCD controller drives up to 4 commons and 32 segments directly. ## PSoC 5 vs PSoC 6 — what the Cortex-M4 peer changes The CY8C6137BZI-F54 runs a Cortex-M4 at 150 MHz with 104 I/O and a 1.7 V supply — it is not a pin-drop replacement. The 68-QFN footprint of the CY8C5867LTI-LP025 does not map to the PSoC 6's 124-ball BGA; a board spin is required. For a BOM that already qualifies the CY8C5867LTI-LP025, the Cortex-M3 part remains the correct fit unless the application needs the M4's DSP extension or the higher I/O count.","metaTitle":"Infineon CY8C5867LTI-LP025 PSoC 5 MCU, 67 MHz, 128 KB Flash","metaDescription":"Active-production CY8C5867LTI-LP025 ARM Cortex-M3 MCU, 67 MHz, 128 KB flash, 32 KB SRAM, 2 KB EEPROM, CapSense, 20-bit ADC, 68-QFN.","metaKeywords":null},"attributes":{"series":"PSOC® 5 CY8C58LP","packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Microcontrollers & Processors (MCU / MPU / DSP)"],"specifications":{"Speed":"67MHz","Series":"PSOC® 5 CY8C58LP","Package":"Tray","RAM Size":"32K x 8","Core Size":"32-Bit Single-Core","EEPROM Size":"2K x 8","Peripherals":"CapSense, DMA, LCD, POR, PWM, WDT","Connectivity":"I²C, LINbus, SPI, UART/USART","Mounting Type":"Surface Mount","Number of I/O":"38","Core Processor":"ARM® Cortex®-M3","Package / Case":"68-VFQFN Exposed Pad","Data Converters":"A/D 1x20b, 1x12b; D/A 4x8b","Oscillator Type":"Internal","lifecycle_stage":"eol_hot","Program Memory Size":"128KB (128K x 8)","Program Memory Type":"FLASH","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"68-QFN (8x8)","Voltage - Supply (Vcc/Vdd)":"1.71V ~ 5.5V"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$21.52","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$21.52000","currency":"USD"},{"qty":10,"price":"$19.84800","currency":"USD"},{"qty":25,"price":"$18.95560","currency":"USD"},{"qty":80,"price":"$16.94863","currency":"USD"},{"qty":260,"price":"$16.16808","currency":"USD"},{"qty":520,"price":"$15.38756","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/a97cb01a4a76dfb721d7373e1fe0e04c.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the closest functional second-source to the CY8C5867LTI-LP025?","answer":"The CY8C6137BZI-F54 is a PSoC 6 Cortex-M4 part running at 150 MHz with 104 I/O, but it uses a 124-ball BGA package — the 68-QFN footprint of the CY8C5867LTI-LP025 is not compatible. The 20-bit ADC and 4x8-bit DAC on the CY8C5867LTI-LP025 are not present on the PSoC 6 peer. A board spin is required to migrate."},{"question":"What compliance documentation does Infineon provide for the CY8C5867LTI-LP025?","answer":"Infineon confirms ROHS3 compliance for this part. Standard documentation includes the datasheet, application notes, and the PSoC Creator IDE with component datasheets."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY8C5867LTI-LP025","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY8C5867LTI-LP025 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-22T19:45:10.375Z","lastPublished":"2026-07-22T19:45:10.375Z","indexable":true}}