{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C4121KV13-667FCXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C4121KV13-667FCXC","canonicalUrl":"https://icboms.com/infineon/CY7C4121KV13-667FCXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C4121KV13-667FCXC","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C4121KV13-667FCXC, QDR IV synchronous SRAM, 144 Mbit, 8M×18, 667 MHz clock, 361-FCBGA (21×21 mm), 1.26V–1.34V supply, 0°C–70°C.","salesMarkdown":"## What this QDR IV SRAM brings to a high-throughput design It is designed for applications that demand sustained read and write bandwidth with no dead cycles between bus turns — think network switch buffers, test-and-measurement acquisition memory, and high-end compute accelerators where the memory interface is the bottleneck. The 667 MHz clock rate on a QDR IV interface delivers four data words per clock cycle (two reads and two writes), effectively quadrupling the throughput compared to a single-data-rate SRAM at the same frequency. This is a part selected when a DDR3 or RLDRAM cannot match the random-access latency profile needed for look-up tables or flow-control state. The 1.26 V to 1.34 V supply range is a dedicated core rail that should be clean and well-decoupled. ## Package and physical integration Housed in a 361-ball FCBGA (21×21 mm footprint) with a surface-mount interface. The fine-pitch BGA requires controlled impedance routing for the parallel bus and adequate decoupling capacitance distributed across the ball field — a 4-layer or 6-layer PCB is typical. The Tray shipping medium is standard for BGA devices; no reel option is listed. This removes the last-time-buy urgency for new designs.","metaTitle":"Cypress CY7C4121KV13-667FCXC 144 Mbit QDR IV SRAM, 667 MHz","metaDescription":"Cypress CY7C4121KV13-667FCXC 144 Mbit QDR IV synchronous SRAM, 667 MHz clock, 361-FCBGA, 1.26V–1.34V supply, 8M×18 organization, 0°C–70°C. Active lifecycle.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, QDR IV","Memory Size":"144Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"361-BBGA, FCBGA","Product Status":"Active","Clock Frequency":"667 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.26V ~ 1.34V","Base Product Number":"CY7C4121","Memory Organization":"8M x 18","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"361-FCBGA (21x21)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$218.5000","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/aa2aaa8260c5ac480807fe5c151e630a.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Where can I buy CY7C4121KV13-667FCXC and what is the lead time?","answer":"Submit an RFQ for current pricing and lead-time confirmation — availability is verified at quote time, not listed on the page."},{"question":"What is the memory organization of CY7C4121KV13-667FCXC?","answer":"Organized as 8M words by 18 bits (8M x 18), yielding 144 Mbit total. The QDR IV interface provides separate read and write ports for simultaneous access."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C4121KV13-667FCXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C4121KV13-667FCXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}