{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C25682KV18-550BZXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C25682KV18-550BZXC","canonicalUrl":"https://icboms.com/infineon/CY7C25682KV18-550BZXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C25682KV18-550BZXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C25682KV18-550BZXC synchronous SRAM, DDR II+, 72Mbit, 4M x 18 organization, 550 MHz clock, 1.7V-1.9V supply, 165-FBGA (13x15), tray.","salesMarkdown":"## 72 Mbit DDR II+ SRAM at 550 MHz The CY7C25682KV18-550BZXC is a 72 Mbit synchronous SRAM from Infineon, organized as 4M x 18 bits and built on DDR II+ technology. The 550 MHz clock rate means the memory delivers double-data-rate transfers on both edges of the clock, effectively doubling the data throughput per pin compared to a single-data-rate part at the same frequency. Operates from a single 1.7 V to 1.9 V supply rail — a narrow window that keeps the I/O levels compatible with low-voltage ASICs and FPGAs without needing a separate VDDQ rail. The parallel memory interface routes 18 data lines plus address and control; the 550 MHz edge rate demands careful signal-integrity layout with matched trace lengths and proper termination on the data strobes.","metaTitle":"CY7C25682KV18-550BZXC Infineon 72Mbit SRAM, 550 MHz","metaDescription":"Infineon CY7C25682KV18-550BZXC 72Mbit synchronous SRAM, DDR II+, 550 MHz clock, 4M x 18 organization, 165-FBGA. Active production, sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Packaging":"Tray","Technology":"SRAM - Synchronous, DDR II+","Memory Size":"72Mbit","Memory Type":"Volatile","Part Status":"Active","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Clock Frequency":"550 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C25682","Memory Organization":"4M x 18","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"165-FBGA (13x15)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$355.5400","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/f19132fc37b3d01e4f681995de6fd1cb.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C25682KV18-550BZXC/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization and interface of this SRAM?","answer":"Organized as 4M x 18 bits (72 Mbit total) with a parallel interface. The DDR II+ architecture transfers data on both clock edges at 550 MHz, giving a peak data rate of 1.1 G transfers per second per pin."},{"question":"What package does CY7C25682KV18-550BZXC use and how is it supplied?","answer":"This is standard for BGA memory devices; the tray format is typical for volume assembly where the parts are picked and placed directly from the tray."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C25682KV18-550BZXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C25682KV18-550BZXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}