{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C25652KV18-400BZXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C25652KV18-400BZXI","canonicalUrl":"https://icboms.com/infineon/CY7C25652KV18-400BZXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C25652KV18-400BZXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C25652KV18-400BZXI, synchronous QDR II+ SRAM, 72 Mbit, 2M x 36 organization, 400 MHz clock, 1.7-1.9 V supply, -40°C to 85°C, 165-LBGA tray.","salesMarkdown":"## 72 Mbit QDR II+ SRAM at 400 MHz — what the clock buys you The CY7C25652KV18-400BZXI is a 72 Mbit synchronous QDR II+ SRAM organized as 2M x 36. The 400 MHz clock rate means the memory delivers a peak data rate of 1.6 Gbps per I/O pin using the quad-data-rate architecture — two read and two write ports per clock cycle. This suits high-throughput applications like network packet buffers, line cards, and test equipment where the SRAM must keep up with the ASIC or FPGA without wait states. ## Industrial temperature and supply tolerance The 1.7 V to 1.9 V supply rail gives the board designer headroom: a 1.8 V nominal rail with ±5 % tolerance stays within the operating window, and the core logic is compatible with 1.8 V I/O standards common in high-performance FPGAs and network processors. Supplied in a 165-ball LBGA (13x15 mm FBGA), the 1.0 mm ball pitch requires a standard 4-layer or 6-layer PCB with via-in-pad for the inner rows. The footprint is identical to other 165-ball QDR II+ SRAMs from Cypress/Infineon, so a single board layout can accommodate density upgrades without a respin. The tray packaging is typical for volume assembly — no reel, so plan for pick-and-place feeder changeover.","metaTitle":"Infineon CY7C25652KV18-400BZXI QDR II+ SRAM, 72Mbit, 400 MHz","metaDescription":"Active QDR II+ SRAM, 72Mbit (2M x 36), 400 MHz clock, 1.7-1.9V, -40 to 85°C, 165-FBGA. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"title":"CY7C25652KV18-400BZXI","Package":"Tray","Technology":"SRAM - Synchronous, QDR II+","Memory Size":"72Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Clock Frequency":"400 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C25652","Memory Organization":"2M x 36","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"165-FBGA (13x15)"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$196.7200","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/438a7d74bdeae93b13fd3b69bda25679.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory organization of CY7C25652KV18-400BZXI?","answer":"It is organized as 2M words by 36 bits, giving a total density of 72 Mbit. The 36-bit data bus is typically used with a 32-bit data word plus 4 bits for ECC or sideband control."},{"question":"What voltage does CY7C25652KV18-400BZXI require?","answer":"The supply voltage range is 1.7 V to 1.9 V, making it a 1.8 V nominal device. The I/O interface is also 1.8 V HSTL-compatible."},{"question":"Is CY7C25652KV18-400BZXI RoHS compliant?","answer":"The device is supplied in a RoHS-compliant tray package. Infineon provides full material declaration and RoHS/REACH certificates upon request."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C25652KV18-400BZXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C25652KV18-400BZXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}