{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C2265XV18-633BZXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C2265XV18-633BZXC","canonicalUrl":"https://icboms.com/infineon/CY7C2265XV18-633BZXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C2265XV18-633BZXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C2265XV18-633BZXC QDR II+ synchronous SRAM, 36Mbit (1M x 36), 633 MHz clock, 1.7-1.9V supply, 165-FBGA (13x15mm), commercial temp, tray.","salesMarkdown":"## QDR II+ SRAM for high-throughput data paths The CY7C2265XV18-633BZXC is a 36 Mbit synchronous SRAM built on Quad Data Rate II+ (QDR II+) architecture, organized as 1M x 36. The 633 MHz clock rate delivers two data transfers per clock edge on both read and write ports, giving a peak bandwidth of 2.5 Gbytes/s per device — a fit for packet buffers in network line cards, radar signal processing, and oscilloscope acquisition memories where the FPGA or ASIC needs a wide, fast scratchpad. The 165-FBGA package (13x15 mm body, 1.0 mm ball pitch) requires a multi-layer PCB with microvia fan-out under the BGA footprint. The ball map is standard for QDR II+ 165-ball devices, so the layout can be reused across density upgrades within the family without a board spin.","metaTitle":"Infineon CY7C2265XV18-633BZXC QDR II+ SRAM, 36Mbit, 633 MHz","metaDescription":"Infineon CY7C2265XV18-633BZXC QDR II+ synchronous SRAM, 36Mbit (1M x 36), 633 MHz clock, 1.7-1.9V, 165-FBGA. Active lifecycle. Sourced to order per RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, QDR II+","Memory Size":"36Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Active","Clock Frequency":"633 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C2265","Memory Organization":"1M x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"165-FBGA (13x15)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$100.8125","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/f51ca91a1ebd4eb3be938d041bd3c775.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C2265XV18-633BZXC/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization and interface of CY7C2265XV18-633BZXC?","answer":"It is organized as 1M x 36 bits with a parallel interface. The QDR II+ architecture provides separate read and write ports, each operating at double data rate on both edges of the 633 MHz clock."},{"question":"What package does CY7C2265XV18-633BZXC use?","answer":"The device is supplied in a 165-ball FBGA package (13x15 mm body). It ships in tray packaging, not tape-and-reel."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C2265XV18-633BZXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C2265XV18-633BZXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}