{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1911KV18-333BZC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1911KV18-333BZC","canonicalUrl":"https://icboms.com/infineon/CY7C1911KV18-333BZC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1911KV18-333BZC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1911KV18-333BZC QDR II synchronous SRAM, 18 Mbit (2M x 9), 333 MHz clock, parallel interface, 1.7V–1.9V supply, 0°C–70°C, 165-FBGA (13x15 mm), tray.","salesMarkdown":"## 333 MHz QDR II SRAM — bandwidth and bus-fit The CY7C1911KV18-333BZC is an 18 Mbit QDR II synchronous SRAM from Infineon, organized as 2M x 9. The 333 MHz clock rate means the device delivers a peak data rate of 666 MHz on the data bus (double-data-rate on reads and writes), which is the figure that governs the throughput ceiling in a high-speed buffer or cache application. QDR II (Quad Data Rate) architecture separates the read and write data ports, eliminating the bus-turnaround penalty that standard synchronous SRAMs incur when switching between read and write cycles. For a network processor or ASIC that streams packets in and out simultaneously, this keeps the bus fully utilized. Core supply is 1.7 V to 1.9 V (nominal 1.8 V), a narrow window that demands a clean rail — a switching regulator with <10 mV ripple is typical, and the decoupling cap placement within 2 mm of each VDD pin is standard practice for this speed grade. This limits the part to indoor, controlled-environment equipment — telecom central office, data-center line cards, or benchtop test gear. Not suitable for outdoor or extended-temperature industrial enclosures without active cooling. ## Active lifecycle — no design-in risk No pin-compatible second-source or official successor is recorded — the BOM line is single-sourced to this order code.","metaTitle":"CY7C1911KV18-333BZC QDR II SRAM, 18 Mbit, 333 MHz, 165-FBGA","metaDescription":"Active Infineon CY7C1911KV18-333BZC QDR II synchronous SRAM, 18 Mbit (2M x 9), 333 MHz clock, 1.7V–1.9V, 165-FBGA.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, QDR II","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Active","Clock Frequency":"333 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C1911","Memory Organization":"2M x 9","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"165-FBGA (13x15)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$40.8800","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/66c682634920522619c3dfcc3a818445.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory organization and interface of CY7C1911KV18-333BZC?","answer":"It is an 18 Mbit QDR II synchronous SRAM organized as 2M x 9, with a parallel interface. The 333 MHz clock delivers double-data-rate transfers on separate read and write ports."},{"question":"Where can I buy CY7C1911KV18-333BZC or check stock?","answer":"This part is sourced to order through independent distribution."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1911KV18-333BZC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1911KV18-333BZC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}