{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1645KV18-450BZXI","brand":"Cypress Semiconductor Corp","brandSlug":"cypress-semiconductor-corp","productSlug":"CY7C1645KV18-450BZXI","canonicalUrl":"https://icboms.com/cypress-semiconductor-corp/CY7C1645KV18-450BZXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1645KV18-450BZXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1645KV18-450BZXI, 144Mbit QDR II+ synchronous SRAM, 450 MHz clock, 4M x 36 organization, parallel interface, 1.7 V supply, 165-FBGA (15x17 mm), -40 to 85 °C industrial temperature grade.","salesMarkdown":"The Infineon CY7C1645KV18-450BZXI is a 144Mbit synchronous SRAM built on the QDR II+ architecture, clocked at 450 MHz with a 4M x 36 memory organization. QDR II+ eliminates the bus-turnaround dead cycles that plague conventional SRAM when switching between reads and writes — the data bus stays at full utilization on back-to-back transactions. The 36-bit wide data bus pairs naturally with a 36-bit FPGA or ASIC I/O bank running at 1.7 V to 1.9 V supply range. Typical deployment is in high-bandwidth packet buffers for network switches, base station line cards, or test equipment where deterministic latency and sustained throughput are non-negotiable. ## Package and footprint — 165-FBGA (15x17 mm) Supplied in a 165-ball FBGA, body size 15x17 mm. Surface-mount only. The ball map is specific to the 144Mbit x36 QDR II+ die; a 72Mbit x18 part like the CY7C1543KV18-400BZI uses a different FBGA footprint and will not align on the same PCB land pattern. Verify the layout against the Infineon package drawing before committing the board — the 15x17 mm form factor is not universal across the density range.","metaTitle":"Infineon CY7C1645KV18-450BZXI QDR II+ SRAM, 144Mbit 450 MHz","metaDescription":"Infineon CY7C1645KV18-450BZXI synchronous SRAM, 144Mbit QDR II+, 450 MHz clock, 4M x 36 parallel interface, 1.7 V supply, 165-FBGA, -40 to 85 °C industrial temp. Available to order","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"title":"CY7C1645KV18-450BZXI","Package":"Bulk","Technology":"SRAM - Synchronous, QDR II+","Memory Size":"144Mbit","Memory Type":"Volatile","description":"Infineon CY7C1645KV18-450BZXI synchronous SRAM, 144Mbit, 450 MHz, 1.7 V, 4M x 36 organization, parallel interface, 165FBGA, -40 to 85 °C.","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Clock Frequency":"450 MHz","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C1645","Memory Organization":"4M x 36","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"165-FBGA (15x17)"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$449.2200","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/83052c810355ede007da9e962500af42.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1645KV18-450BZXI/alternatives.json"},"ai":{"faq":[{"question":"What is the closest functional second-source to CY7C1645KV18-450BZXI?","answer":"The CY7C1543KV18-400BZI is the same QDR II+ family but half the density (72Mbit, 4M x 18) and clocked at 400 MHz. It is not a pin-compatible drop-in; however, two CY7C1543s can be width-expanded to match the 36-bit bus if the memory controller supports dual-chip select."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/cypress-semiconductor-corp/CY7C1645KV18-450BZXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/cypress-semiconductor-corp/CY7C1645KV18-450BZXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-16T10:39:33.080Z","lastPublished":"2026-07-16T10:39:33.080Z","indexable":true}}