{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1625KV18-250BZXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1625KV18-250BZXC","canonicalUrl":"https://icboms.com/infineon/CY7C1625KV18-250BZXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1625KV18-250BZXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies QDR II synchronous SRAM, CY7C1625KV18-250BZXC, 144Mbit (16M x 9), 250 MHz clock, 1.7V–1.9V supply, 165-FBGA (15x17 mm), tray.","salesMarkdown":"## 144 Mbit QDR II buffer — clock rate and organization The CY7C1625KV18-250BZXC is a 144 Mbit Quad Data Rate II synchronous SRAM organized as 16M x 9. The 250 MHz clock delivers a peak data rate of 1 Gbps per I/O pin (double-data-rate on both read and write ports), making it suited for high-throughput buffer applications in network switches, routers, and telecom line cards where the QDR II architecture eliminates the read-write bus-turnaround penalty of conventional SRAM. The 9-bit-wide data bus (8 data bits plus one parity bit per word) matches the word width of common network packet processors and search engines that expect a parity lane alongside the data path. ## 165-ball FBGA — board integration demands Housed in a 165-ball fine-pitch BGA (15x17 mm body, 1.0 mm ball pitch), this SRAM requires a multi-layer PCB with controlled-impedance traces for the 250 MHz clock and data lines. The 1.7V–1.9V core supply is a single 1.8 V nominal rail — no separate VDDQ supply is needed, which simplifies the power-tree design compared to earlier QDR generations that used split VDD/VDDQ. ## Active lifecycle — sourcing posture Supplied in tray packaging (standard for BGA devices in prototype and low-to-medium volume builds). For reel/tape quantities, confirm the alternate order code with your sourcing desk.","metaTitle":"Infineon CY7C1625KV18-250BZXC QDR II SRAM, 144Mbit, 250 MHz","metaDescription":"Infineon CY7C1625KV18-250BZXC QDR II synchronous SRAM, 144Mbit (16M x 9), 250 MHz clock. Active lifecycle, 165-FBGA. Sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, QDR II","Memory Size":"144Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Active","Clock Frequency":"250 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C1625","Memory Organization":"16M x 9","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"165-FBGA (15x17)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$307.6850","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/887d88dfd918fb0b22dd519b20ee4bb4.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory organization and clock speed of CY7C1625KV18-250BZXC?","answer":"It is a 144 Mbit QDR II synchronous SRAM organized 16M x 9, clocked at 250 MHz. The QDR II architecture provides independent read and write ports, each operating at double data rate, for a peak throughput of 1 Gbps per I/O pin."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1625KV18-250BZXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1625KV18-250BZXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}