{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1512KV18-300BZC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1512KV18-300BZC","canonicalUrl":"https://icboms.com/infineon/CY7C1512KV18-300BZC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1512KV18-300BZC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1512KV18-300BZC, QDR II synchronous SRAM, 72Mbit (4M x 18), 300 MHz clock, 1.7V–1.9V supply, 165-FBGA (13x15), 0°C to 70°C, Tray.","salesMarkdown":"## 72 Mbit QDR II SRAM — 300 MHz bus performance for high-throughput designs It clocks at 300 MHz. At 300 MHz, the QDR II architecture clocks data on both edges. The parallel interface keeps latency deterministic. ## Last Buy — sourcing window is closing","metaTitle":"Infineon CY7C1512KV18-300BZC 72Mbit QDR II SRAM, 300 MHz","metaDescription":"Infineon CY7C1512KV18-300BZC 72Mbit QDR II synchronous SRAM, 300 MHz clock, 1.7-1.9V, 165-FBGA. Last Buy — sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Last Buy","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, QDR II","Memory Size":"72Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Last Time Buy","Clock Frequency":"300 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C1512","Memory Organization":"4M x 18","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"165-FBGA (13x15)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$119.7600","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/5ac29da9241a05bfb6045ef3b50bb4b7.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1512KV18-300BZC/alternatives.json"},"ai":{"faq":[{"question":"Is CY7C1512KV18-300BZC obsolete or last buy?","answer":"Yes, Infineon has classified this part as Last Buy. The manufacturer's final production run is underway; after the LTB cutoff date, no new factory orders will be accepted. Sourcing now through independent distribution is the path to secure inventory."},{"question":"What is the replacement or equivalent for CY7C1512KV18-300BZC?","answer":"No official replacement or successor order code is listed in the available records. For a pin-compatible alternative, the CY7C1512KV18-300BZX shares the same base product number and QDR II architecture — verify the suffix differences against the datasheet before substituting. If a direct drop-in is required, the best approach is to source remaining Last Buy stock."},{"question":"Where can I buy CY7C1512KV18-300BZC and what is the stock status?","answer":"This part is sourced to order against an RFQ through independent distribution. Availability and current pricing are confirmed at quote time. No stock count or lead-time number is published here because the supply position changes daily as Last Buy inventory is consumed."},{"question":"What is CY7C1512KV18-300BZC's technology and memory organization?","answer":"It is a QDR II synchronous SRAM with 72 Mbit density organized as 4M x 18. The QDR II architecture uses separate read and write data ports to eliminate bus-turnaround dead cycles, making it suitable for high-throughput applications like network packet buffers and FPGA cache."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1512KV18-300BZC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1512KV18-300BZC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}