{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1480BV33-167AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1480BV33-167AXC","canonicalUrl":"https://icboms.com/infineon/CY7C1480BV33-167AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1480BV33-167AXC","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C1480BV33-167AXC synchronous SRAM, 72Mbit, 167 MHz clock, 3.4 ns access, 2M x 36 organization, 100-TQFP (14x20), 3.135–3.6 V supply, 0°C to 70°C.","salesMarkdown":"The 100-TQFP (14x20 mm) surface-mount package places it in high-throughput data-path roles — typically network buffers, telecom line cards, or cache memory in embedded systems where deterministic read/write latency matters more than density. At 167 MHz (6 ns period), that leaves roughly 2.6 ns for PCB trace delay, input setup, and hold — tight but workable with proper signal-integrity layout. The synchronous SDR architecture eliminates dead cycles on back-to-back reads compared to asynchronous SRAM, which matters when the bus is running near its limit. If your design already runs a 166 MHz or 133 MHz memory bus, this part drops in without re-timing the controller. ## 2M x 36 organization — wide-word bus fit The 2M depth by 36-bit width is not a standard 8/16/32-bit memory; it targets systems with a 36-bit data path — common in networking ASICs, telecom framers, or DSP arrays that process 36-bit words (e.g., 32-bit data plus 4-bit parity or ECC). If your controller expects a 32-bit bus, you can tie the upper four data pins low or leave them unconnected, but the 36-bit width is the native fit. The 72 Mbit total density fills a 2M-word address space, so address lines are minimal for the depth. Cypress no longer manufactures it; new orders go through independent distribution as surplus or last-time-buy inventory.","metaTitle":"Cypress CY7C1480BV33-167AXC 72Mbit Sync SRAM, 167 MHz","metaDescription":"Cypress CY7C1480BV33-167AXC synchronous SRAM, 72Mbit, 167 MHz clock, 3.4 ns access, 2M x 36, 100-TQFP, 3.135–3.6 V, 0°C–70°C.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3.4 ns","Memory Size":"72Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"167 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1480","Memory Organization":"2M x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/b45bf413db42550bfdcb3d546b458cdc.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is CY7C1480BV33-167AXC obsolete?","answer":"Yes, the lifecycle status is obsolete. Cypress no longer produces this part; it is available only through surplus or broker channels."},{"question":"What is the access time of CY7C1480BV33-167AXC?","answer":"The access time is 3.4 ns at the 167 MHz clock rate."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1480BV33-167AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1480BV33-167AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}