{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1472V33-200AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1472V33-200AXC","canonicalUrl":"https://icboms.com/infineon/CY7C1472V33-200AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1472V33-200AXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ synchronous SRAM, CY7C1472V33-200AXC, 72Mbit (4M x 18), 200 MHz clock, 3 ns access time, 3.3 V supply, 100-LQFP tray.","salesMarkdown":"## NoBL pipeline — why the dead bus cycle disappears The CY7C1472V33-200AXC is a 72 Mbit synchronous SRAM from Infineon's NoBL (No Bus Latency) family, organized 4 M x 18. The NoBL pipeline lets the memory accept a new read or write address on every clock edge without inserting idle cycles between bus-turn operations — a standard synchronous SRAM stalls one cycle when switching from read to write, but this part keeps the bus full at 200 MHz. That 200 MHz clock rate, combined with the 3 ns access time, delivers a peak random-access bandwidth of 400 MB/s on a 32-bit data bus (or 450 MB/s on the native 18-bit word). The 3 ns figure is the first-word latency from address assertion to data valid; subsequent words in a burst follow at the clock rate. A switching regulator feeding this SRAM should stay within 3.3 V ± 0.165 V at the device pins; a linear regulator with 200 mV dropout is marginal if the input rail is 3.3 V. This part is specified for indoor equipment — telecom central-office switches, base-station line cards, network routers, and test equipment — not for outdoor or under-hood deployment. The 100-TQFP package (14 x 20 mm, 0.5 mm pitch) requires a 4-layer PCB for fan-out of the inner rows; the exposed pad is not present on this package, so thermal relief is through the leads alone.","metaTitle":"CY7C1472V33-200AXC Infineon NoBL SRAM, 72Mbit, 200 MHz","metaDescription":"CY7C1472V33-200AXC synchronous SRAM, 72Mbit (4Mx18), 200 MHz clock, 3 ns access. Active production. Request quote for pricing and lead time.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3 ns","Memory Size":"72Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"200 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1472","Memory Organization":"4M x 18","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$128.6129","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/63555aa8b5a6d221e163fecee1a9e074.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1472V33-200AXC/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization of CY7C1472V33-200AXC?","answer":"The memory is organized as 4 M words by 18 bits (72 Mbit total). The 18-bit word width supports a byte-parity or ECC-protected data bus where one bit per word carries the parity or check code."},{"question":"What package does CY7C1472V33-200AXC come in?","answer":"The supplier device package is 100-TQFP (14x20). The part is supplied in trays."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1472V33-200AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1472V33-200AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}