{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1471BV33-133AXCT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1471BV33-133AXCT","canonicalUrl":"https://icboms.com/infineon/CY7C1471BV33-133AXCT","factsUrl":"https://icboms.com/api/mcp/products/CY7C1471BV33-133AXCT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1471BV33-133AXCT, NoBL™ Synchronous SRAM, 72Mbit (2M x 36), 133 MHz clock frequency, 6.5 ns access time, 3.135V–3.6V supply, 100-TQFP (14x20), 0°C–70°C operating temperature, Tape & Reel.","salesMarkdown":"## 72Mbit NoBL SRAM for high-throughput data paths It runs at a 133 MHz clock with a 6.5 ns access time, meaning the memory can deliver a new 36-bit word every clock cycle without inserting dead cycles between read and write turns. The 36-bit word width is worth noting — it maps cleanly to a 32-bit datapath with four parity bits, or to a 36-bit wide memory bus without external byte-lane muxing. Supply range is 3.135V to 3.6V, which aligns with standard 3.3V logic families. ## 6.5 ns access — timing margin for the system architect At a 133 MHz clock (7.5 ns period), this leaves about 1 ns of setup margin before the next rising edge — tight but workable with controlled impedance traces and matched-length routing on the address/control bus. If your FPGA or ASIC interface has a setup time of 1.5 ns or more, you may need to add a wait state or reduce clock frequency. Budget the PCB flight time and clock skew into that margin. ## No Bus Latency — what it saves you Standard synchronous SRAMs insert one dead cycle when switching from read to write (or write to read). The NoBL architecture eliminates that turnaround penalty, so a read immediately followed by a write completes in two clocks instead of three. In a 133 MHz system that saves 7.5 ns per transaction — meaningful for burst-oriented traffic like cache line fills or descriptor ring updates. Housed in a 100-lead TQFP (14x20 mm body), the part is surface-mount and suited for standard reflow assembly. That means no last-time-buy pressure for ongoing builds.","metaTitle":"CY7C1471BV33-133AXCT NoBL SRAM, 72Mbit, 133 MHz, 6.5 ns","metaDescription":"Infineon CY7C1471BV33-133AXCT NoBL synchronous SRAM, 72Mbit (2M x 36), 133 MHz clock, 6.5 ns access time, 100-TQFP.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tape & Reel (TR)","Technology":"SRAM - Synchronous, SDR","Access Time":"6.5 ns","Memory Size":"72Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1471","Memory Organization":"2M x 36","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$172.5500","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/628924c755bdff75b315179b2f6927ff.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1471BV33-133AXCT/alternatives.json"},"ai":{"faq":[],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1471BV33-133AXCT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1471BV33-133AXCT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}