{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1470BV33-200BZC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1470BV33-200BZC","canonicalUrl":"https://icboms.com/infineon/CY7C1470BV33-200BZC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1470BV33-200BZC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ Synchronous SRAM, 72Mbit, 2M x 36 organization, 200 MHz clock, 3 ns access time, 3.135V–3.6V supply, 165-FBGA (15x17), Tray.","salesMarkdown":"## 72Mbit NoBL synchronous SRAM — 200 MHz pipeline The CY7C1470BV33-200BZC is a 72 Mbit synchronous SRAM organized as 2M x 36, built on Infineon's NoBL (No Bus Latency) architecture. It clocks at 200 MHz with a 3 ns access time from the clock edge, meaning the read data appears on the bus within one clock cycle of the address — no dead cycles between read and write turns. This is a volatile, SDR (single data rate) SRAM with a parallel memory interface, supplied from a 3.135 V to 3.6 V rail. ## Package and board-fit — 165-ball FBGA Housed in a 165-ball LBGA (supplier device package 165-FBGA, 15x17 mm), this is a fine-pitch BGA that requires a multilayer PCB for fan-out.","metaTitle":"CY7C1470BV33-200BZC NoBL SRAM, 72Mbit, 200 MHz, 165-FBGA","metaDescription":"Infineon CY7C1470BV33-200BZC NoBL synchronous SRAM, 72Mbit (2M x 36), 200 MHz clock, 3 ns access, 165-FBGA. Obsolete — sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3 ns","Memory Size":"72Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Obsolete","Clock Frequency":"200 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1470","Memory Organization":"2M x 36","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"165-FBGA (15x17)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$127.9900","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/83307e304e9f2bc3dc3842e011f87753.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1470BV33-200BZC/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization of CY7C1470BV33-200BZC?","answer":"2M x 36 — 2,097,152 words of 36 bits each, for a total of 72 Mbit. The 36-bit word width suits systems with 32-bit data plus parity or ECC overhead."},{"question":"What package does CY7C1470BV33-200BZC use?","answer":"165-ball LBGA (low-profile ball grid array), supplier device package 165-FBGA with a 15x17 mm body. The balls are on a 1.0 mm pitch."},{"question":"What supply voltage does CY7C1470BV33-200BZC require?","answer":"3.135 V to 3.6 V, with a nominal 3.3 V rail. All I/O are 3.3 V tolerant — no level translation needed when interfacing to a 3.3 V controller or FPGA bank."},{"question":"What is the clock frequency and access time?","answer":"200 MHz maximum clock frequency. The access time from the rising clock edge is 3 ns — the data is valid on the bus within one cycle of the address being registered."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1470BV33-200BZC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1470BV33-200BZC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:10:32.143Z","lastPublished":"2026-07-21T02:10:32.143Z","indexable":true}}