{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1462AV33-200AXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1462AV33-200AXI","canonicalUrl":"https://icboms.com/infineon/CY7C1462AV33-200AXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1462AV33-200AXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon NoBL™ CY7C1462AV33-200AXI, 36Mbit Synchronous SRAM, 2M x 18 organization, 200 MHz clock frequency, 3.2 ns access time, Parallel interface, 3.135V ~ 3.6V supply, -40°C ~ 85°C, 100-LQFP.","salesMarkdown":"## 36 Mbit synchronous SRAM with NoBL flow-through The NoBL architecture eliminates the dead cycle between read and write operations, letting the bus switch direction on consecutive clock edges without an idle turn-around cycle. This matters for designs that interleave read and write accesses — a network packet buffer or a cache line fill, for example — where every lost cycle costs throughput. ## Industrial temperature grade and 100-pin LQFP The 100-LQFP package (supplier device package 100-TQFP 14x20 mm) is a surface-mount, fine-pitch footprint. Infineon lists the CY7C1462AV33-200AXI as obsolete. No last-time-buy window or official successor appears in the current record.","metaTitle":"CY7C1462AV33-200AXI 36Mbit NoBL SRAM, 200 MHz, 3.2 ns","metaDescription":"Infineon CY7C1462AV33-200AXI 36Mbit synchronous SRAM with NoBL architecture, 200 MHz clock, 3.2 ns access time, industrial temp.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3.2 ns","Memory Size":"36Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"200 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1462","Memory Organization":"2M x 18","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/bdbf9409b3e2555267d0abfd02f718e8.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1462AV33-200AXI/alternatives.json"},"ai":{"faq":[{"question":"What is the access time of CY7C1462AV33-200AXI?","answer":"The CY7C1462AV33-200AXI has a 3.2 ns access time at a 200 MHz clock frequency. That 3.2 ns window covers address-to-data-out and clock-to-data-out paths, so the memory can deliver a new data word every 5 ns clock cycle. The NoBL architecture means the bus does not waste a cycle when switching from read to write — the 3.2 ns access still holds on the first read after a write."},{"question":"Where can I buy CY7C1462AV33-200AXI?","answer":"Submit an RFQ for current availability and pricing — each quote is confirmed at order time. Because the part is obsolete, stock is limited to existing inventory in the supply chain; no factory lead time applies."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1462AV33-200AXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1462AV33-200AXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}