{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1460KV33-250AXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1460KV33-250AXI","canonicalUrl":"https://icboms.com/infineon/CY7C1460KV33-250AXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1460KV33-250AXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1460KV33-250AXI, NoBL™ Synchronous SRAM, 36Mbit (1M x 36), 250 MHz clock, 2.5 ns access, Parallel interface, 3.135V–3.6V supply, -40°C to 85°C, 100-TQFP (14x20), Tray.","salesMarkdown":"## Active production, 250 MHz NoBL SRAM for wide-bus throughput It delivers a 250 MHz clock frequency with a 2.5 ns access time, eliminating the dead cycle between read and write operations that standard pipelined SRAMs require. ## NoBL architecture — what the 250 MHz clock buys you Standard synchronous SRAMs insert a turnaround cycle when switching from read to write, wasting a clock edge. The NoBL pipeline lets the bus transition without a dead cycle, so at 250 MHz the effective data rate approaches the full clock rate on mixed read/write traffic. For a 36-bit-wide bus, that is 9 Gbit/s of sustained bandwidth — the difference between meeting a line-rate packet buffer budget and falling short by one cycle. At 250 MHz (4 ns period), that leaves 1.5 ns of setup margin before the next clock edge — tight, but workable with controlled-impedance traces and proper termination. The 36-bit organization maps cleanly to a 32-bit data bus plus parity or ECC bits without needing two devices.","metaTitle":"Infineon CY7C1460KV33-250AXI 36Mbit NoBL SRAM, 250 MHz","metaDescription":"Infineon CY7C1460KV33-250AXI 36Mbit NoBL synchronous SRAM, 250 MHz clock, 2.5 ns access, 1M x 36, 100-TQFP, -40 to 85°C.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"2.5 ns","Memory Size":"36Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"250 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1460","Memory Organization":"1M x 36","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$66.4475","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/13209eba2424827fecd044dad8220f00.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1460KV33-250AXI/alternatives.json"},"ai":{"faq":[{"question":"Is the CY7C1460KV33-250AXI RoHS compliant?","answer":"The suffix 'AXI' indicates a lead-free, RoHS-compliant finish (NiPdAu or similar) on the 100-TQFP package. Infineon's standard RoHS declaration applies; no separate compliance certificate is needed for most production lines."},{"question":"Can the CY7C1460KV33-250AXI replace the CY7C1460KV33-250AXC?","answer":"The CY7C1460KV33-250AXC was a leaded (SnPb) version of the same die in the same 100-TQFP package. The 'AXI' suffix is the RoHS-compliant, lead-free variant. They are pin-compatible and functionally identical — the only difference is the solder-ball metallurgy. If your reflow profile supports lead-free, the AXI is a direct drop-in replacement."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1460KV33-250AXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1460KV33-250AXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}