{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1460KV33-200AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1460KV33-200AXC","canonicalUrl":"https://icboms.com/infineon/CY7C1460KV33-200AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1460KV33-200AXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1460KV33-200AXC NoBL™ Synchronous SRAM, 36Mbit (1M x 36), 200 MHz clock frequency, 3.2 ns access time, 3.135V ~ 3.6V supply, 100-LQFP / 100-TQFP (14x20), 0°C to 70°C operating temperature, Tray.","salesMarkdown":"## 36 Mbit NoBL synchronous SRAM — 200 MHz, 3.2 ns access The NoBL architecture eliminates the dead bus cycles typical of traditional synchronous SRAMs by allowing back-to-back read and write operations without turnaround cycles, which directly improves throughput in high-bandwidth applications like network buffers, telecom line cards, and high-end compute accelerators. ## 200 MHz clock and 3.2 ns access — timing budget for the bus The 200 MHz clock rate sets a 5 ns cycle window. The 3.2 ns access time leaves 1.8 ns of slack for the controller's setup and hold, PCB trace delay, and signal-integrity margin. A system architect clocking a 200 MHz memory controller must verify that the combined FPGA/ASIC output delay plus board propagation fits inside that window — otherwise, the next speed grade (if available) or a flow-through pipeline stage is needed. The parallel memory interface (36-bit data bus) matches well with 32-bit or 36-bit controllers; the 1M word depth gives 4 MB of addressable space per chip. The base product number CY7C1460 covers multiple speed and package variants; the -200AXC suffix selects the 200 MHz speed grade in a 100-TQFP (14x20) package, tray delivery. No official successor or second-source alternate is recorded in the sourcing data, so the BOM depends on this exact order code for fit.","metaTitle":"Infineon CY7C1460KV33-200AXC NoBL SRAM, 36Mbit, 200 MHz","metaDescription":"Infineon CY7C1460KV33-200AXC NoBL synchronous SRAM, 36Mbit (1M x 36), 200 MHz clock, 3.2 ns access, 3.135V-3.6V, 100-TQFP, 0°C to 70°C. Active lifecycle.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3.2 ns","Memory Size":"36Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"200 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1460","Memory Organization":"1M x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$48.6184","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/13209eba2424827fecd044dad8220f00.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1460KV33-200AXC/alternatives.json"},"ai":{"faq":[],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1460KV33-200AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1460KV33-200AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}