{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C145-35JXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C145-35JXC","canonicalUrl":"https://icboms.com/infineon/CY7C145-35JXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C145-35JXC","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C145-35JXC, 72Kbit dual-port asynchronous SRAM, 8Kx9 organization, 35ns access time, 4.5-5.5V supply, 68-PLCC (24.23x24.23mm) J-lead surface-mount package, 0 to 70 °C, tray.","salesMarkdown":"## What this dual-port SRAM does and where it fits The Cypress CY7C145-35JXC is a 72Kbit dual-port asynchronous SRAM organized as 8K words by 9 bits. The dual-port architecture allows two independent systems or processors to read from and write to the same memory array simultaneously, each through its own address, data, and control buses. Typical applications include shared memory in multiprocessor systems, FIFO buffers in telecom line cards, and data exchange buffers in industrial controllers where one port connects to a DSP and the other to a host CPU. The 9-bit width accommodates an eighth data bit plus a parity bit, common in 8-bit-plus-parity bus architectures. No official successor order code is listed in the available records. For BOM lines that require this exact dual-port SRAM, the only sourcing channel is the independent surplus and broker market. No production-status claim is made beyond the obsolete designation.","metaTitle":"Cypress CY7C145-35JXC Dual-Port SRAM, 72Kbit, 35ns, 68-PLCC","metaDescription":"Cypress CY7C145-35JXC 72Kbit dual-port asynchronous SRAM, 8Kx9, 35ns access, 4.5-5.5V, 68-PLCC, 0-70°C. Obsolete — sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"title":"CY7C145-35JXC","Package":"Tray","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"35 ns","Memory Size":"72Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"68-LCC (J-Lead)","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C145","Memory Organization":"8K x 9","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"68-PLCC (24.23x24.23)","Write Cycle Time - Word, Page":"35ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/8dd97de2c060a1d7b25f36619d6625aa.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the CY7C145-35JXC's listed technology?","answer":"SRAM — Dual Port, Asynchronous. The dual-port architecture provides two independent read/write ports for simultaneous access by separate bus masters without external arbitration."},{"question":"What package does the CY7C145-35JXC use, and what is the memory organization?","answer":"The part ships in tray and uses a 68-LCC J-lead surface-mount package. The memory organization is 8K × 9, yielding 72 Kbit of volatile dual-port SRAM."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C145-35JXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C145-35JXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}