{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C145-15AXCT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C145-15AXCT","canonicalUrl":"https://icboms.com/infineon/CY7C145-15AXCT","factsUrl":"https://icboms.com/api/mcp/products/CY7C145-15AXCT","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C145-15AXCT, 72Kbit Dual-Port Asynchronous SRAM, 8K x 9 organization, 15 ns access time, Parallel interface, 4.5V ~ 5.5V supply, 80-TQFP (14x14), 0°C~70°C.","salesMarkdown":"## 15 ns dual-port SRAM — the shared-memory bridge The Cypress CY7C145-15AXCT is a 72Kbit dual-port asynchronous SRAM organized as 8K x 9 bits, in an 80-TQFP surface-mount package. Its 15 ns access time lets two independent bus masters read or write the same memory array without wait states, as long as they avoid the same address simultaneously. The 9th bit per word is typically used for parity or a tag flag, which is useful in fault-tolerant or cache-tag designs. ## 8K x 9 organization — why the 9th bit matters The 8K x 9 memory organization is less common than the standard x8 or x16 width. The extra bit per byte is often mapped as a parity bit for single-bit error detection across the shared memory, or as a software-controlled flag for inter-processor semaphore signaling. If your design expects a straight x8 memory map, you will need to account for the 9-bit bus width in the FPGA or ASIC interface logic. The 72Kbit total capacity is modest — sized for a mailbox buffer, a small packet FIFO, or a configuration store shared between two processors, not for bulk data. The CY7C145-15AXCT is officially obsolete per the manufacturer's product status. Cypress (now part of Infineon) no longer manufactures this die. There is no listed direct replacement from the original manufacturer. ## Commercial temperature — indoor equipment only It is not specified for industrial enclosures, outdoor cabinets, or automotive under-hood environments. If your application sees -40°C or +85°C, this part will not meet the temperature rating. ## 80-TQFP footprint — layout notes This is a standard JEDEC footprint, and the land pattern is widely available in PCB layout libraries. The Tape & Reel suffix (CT) indicates it ships on a reel for automated pick-and-place assembly. MSL is typically 3 for this package family — verify the moisture sensitivity level on the reel label before reflow, and bake if the floor-life has been exceeded.","metaTitle":"Cypress CY7C145-15AXCT 72Kbit Dual-Port SRAM, 15 ns","metaDescription":"Cypress CY7C145-15AXCT 72Kbit (8K x 9) dual-port asynchronous SRAM in 80-TQFP. 15 ns access time, 4.5V-5.5V supply, commercial temp.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tape & Reel (TR)","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"15 ns","Memory Size":"72Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"80-LQFP","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C145","Memory Organization":"8K x 9","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"80-TQFP (14x14)","Write Cycle Time - Word, Page":"15ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$21.3300","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/11a5283ca7dd283f841c3b9dcc5b7753.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C145-15AXCT/alternatives.json"},"ai":{"faq":[{"question":"Is the CY7C145-15AXCT obsolete?","answer":"Yes, the CY7C145-15AXCT is listed as obsolete by the manufacturer. Cypress (now Infineon) no longer produces this part. It is not recommended for new designs."},{"question":"What is the memory organization of the CY7C145-15AXCT?","answer":"The memory is organized as 8K words by 9 bits (8K x 9), for a total of 72Kbit. The 9th bit is often used for parity or a tag flag."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C145-15AXCT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C145-15AXCT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}