{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1441KV33-133AXM","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1441KV33-133AXM","canonicalUrl":"https://icboms.com/infineon/CY7C1441KV33-133AXM","factsUrl":"https://icboms.com/api/mcp/products/CY7C1441KV33-133AXM","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1441KV33-133AXM, SRAM - Synchronous, SDR, 36Mbit (1M x 36), Parallel interface, 133 MHz clock, 6.5 ns access, 3.135V ~ 3.6V supply, -55°C ~ 125°C, 100-TQFP (14x20), Tray.","salesMarkdown":"## 36 Mbit synchronous SRAM for wide-bus, high-reliability systems It uses a single-data-rate (SDR) pipeline architecture clocked at 133 MHz, with a 6.5 ns access time from clock rise. At 133 MHz the part delivers a 7.5 ns cycle time. The 6.5 ns access time from the rising clock edge leaves roughly 1 ns of setup margin before the next cycle — tight enough that the board-level trace delay and clock skew must be budgeted during timing closure. This is a pipelined synchronous SRAM: the address is registered on the first clock edge, and data appears on the following edge. There is no asynchronous read path, so the system controller must manage the pipeline latency. ## 1M x 36 organization — wide data bus fit The 36-bit word width maps directly to a 32-bit data bus plus four parity or ECC bits, or to a 36-bit DSP data path without external muxing. The 36 Mbit density suits moderate-depth FIFO buffers, look-up tables, or packet memory in networking equipment. The parallel interface uses standard synchronous control signals (chip enable, write enable, output enable, burst control) — no serialisation overhead. ## Military temperature range — screening for hi-rel programs The 100-TQFP package is a plastic, surface-mount construction — not hermetic — so the buyer should verify that the program's moisture-sensitivity and outgassing requirements accept a plastic package before committing the BOM. The active lifecycle status means no last-time-buy risk for new designs. ## Supply rail and decoupling considerations At 133 MHz the dynamic current draw is significant; the datasheet recommends a 0.1 µF ceramic capacitor per supply pin, placed as close to the package as possible. The 100-TQFP has a 0.5 mm pitch — ensure the PCB fab can route the fine-pitch traces to the SRAM without via stubs that degrade signal integrity on the data bus.","metaTitle":"Infineon CY7C1441KV33-133AXM 36Mbit Sync SRAM, 133 MHz","metaDescription":"Infineon CY7C1441KV33-133AXM synchronous SRAM, 36Mbit (1M x 36), 6.5 ns access, 133 MHz clock, -55°C to 125°C, 100-TQFP. Active lifecycle.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"6.5 ns","Memory Size":"36Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1441","Memory Organization":"1M x 36","Operating Temperature":"-55°C ~ 125°C (TC)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$124.0240","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/a1944aa602d57ad30841b02570472dc3.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1441KV33-133AXM/alternatives.json"},"ai":{"faq":[{"question":"What is the access time of CY7C1441KV33-133AXM?","answer":"The access time from the rising clock edge is 6.5 ns. At a 133 MHz clock (7.5 ns cycle), this leaves approximately 1 ns of setup margin before the next clock edge — budget trace delay and clock skew accordingly."},{"question":"What is a suitable replacement for CY7C1441KV33-133AXM?","answer":"For dual-sourcing, evaluate other 36 Mbit synchronous SRAMs in 100-TQFP with a 3.3 V supply and 133 MHz clock, but verify pinout and timing compatibility against the datasheet before substituting."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1441KV33-133AXM","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1441KV33-133AXM when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}