{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1441KV33-133AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1441KV33-133AXC","canonicalUrl":"https://icboms.com/infineon/CY7C1441KV33-133AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1441KV33-133AXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1441KV33-133AXC synchronous SRAM, 36Mbit (1M x 36), 133 MHz clock, 6.5 ns access, 3.135–3.6 V, 100-LQFP, 0 to 70 °C.","salesMarkdown":"## 36 Mbit synchronous SRAM – 133 MHz, 1M x 36, 6.5 ns access The CY7C1441KV33-133AXC: The 36-bit word width is the key differentiator here – most synchronous SRAMs in this density bin are 32-bit or 18-bit wide, so this part targets designs that need a full 36-bit datapath with parity or ECC without packing two narrower devices. Typical applications include network packet buffers, telecom line-card queues, and high-end FPGA external memory where the controller expects a 36-bit bus. ## 133 MHz clock + 6.5 ns access – where the timing closes At 133 MHz the bus cycle is 7.5 ns, and the 6.5 ns access time leaves just 1 ns of margin for the memory controller to capture data. That is tight – the board-level trace delay, clock skew, and output hold time all eat into that window. For a new design, verify the controller's tSU and tH against the SRAM's tCO and tOH at the 3.135 V corner, not just the typical 3.3 V. The part is synchronous SDR (single data rate), so it latches addresses on each rising clock edge; no DDR-style double-pumping, which keeps the controller interface simpler but halves the peak bandwidth versus a DDR SRAM at the same clock. ## Active lifecycle – no redesign pressure The base product number is CY7C1441; the KV33 suffix indicates the 3.3 V supply variant, and the -133AXC suffix encodes the 133 MHz speed grade and the 100-TQFP (14x20) package. ## 100-pin LQFP – footprint and environment If your system runs in an industrial cabinet, outdoor enclosure, or under-hood automotive application, the 0–70°C rating will not hold – you would need the industrial-temperature variant of this family (typically -40 to 85°C). The mounting is surface mount, and the package ships in a tray.","metaTitle":"CY7C1441KV33-133AXC 36Mbit Sync SRAM, 133 MHz, 6.5 ns","metaDescription":"Infineon CY7C1441KV33-133AXC 36Mbit synchronous SRAM, 1M x 36 organization, 133 MHz clock, 6.5 ns access, 100-LQFP, 0–70°C. Active lifecycle.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"6.5 ns","Memory Size":"36Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1441","Memory Organization":"1M x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$48.5658","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/343e1ed91de8fad7950fb93c4143c364.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1441KV33-133AXC/alternatives.json"},"ai":{"faq":[],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1441KV33-133AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1441KV33-133AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}