{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1426AV18-300BZXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1426AV18-300BZXC","canonicalUrl":"https://icboms.com/infineon/CY7C1426AV18-300BZXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1426AV18-300BZXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1426AV18-300BZXC, 36Mbit QDR II synchronous SRAM, 300 MHz clock, 1.7-1.9 V supply, 165-LBGA (15×17 mm), 4M×9 organization, 0-70 °C, parallel interface, Tray.","salesMarkdown":"## 36Mbit QDR II SRAM — 300 MHz, 1.7–1.9 V, 165-FBGA The CY7C1426AV18-300BZXC is a 36 Mbit Quad Data Rate (QDR) II synchronous SRAM organized as 4M × 9 bits, operating at a 300 MHz clock frequency with a parallel interface. The 1.7 V to 1.9 V supply range aligns with low-voltage memory buses common in networking and telecom line-card designs. Packaged in a 165-ball LBGA (15 × 17 mm), the device is surface-mount and supplied in tray format. ## QDR II bus architecture and throughput QDR II architecture delivers four data words per clock cycle — two on the rising edge and two on the falling edge of both the K and K# clocks — yielding a peak data rate of 1.2 Gbps per I/O pin at 300 MHz. This burst-oriented interface is designed for applications requiring high random-access throughput with separate read and write ports, eliminating bus-turnaround cycles. The 4M × 9 organization provides a 9-bit-wide data path (8 data bits plus one parity/ECC bit), commonly used in packet-buffer and lookup-table designs where the extra bit supports error detection without external logic. ## Lifecycle status and sourcing Infineon lists the CY7C1426AV18-300BZXC as Obsolete. No pin-compatible direct replacement from the original manufacturer is documented. For existing BOM lines, the 165-FBGA footprint and 1.7–1.9 V supply rail are the critical fit parameters.","metaTitle":"CY7C1426AV18-300BZXC 36Mbit QDR II SRAM, 300 MHz, 165-FBGA","metaDescription":"Infineon CY7C1426AV18-300BZXC 36Mbit QDR II synchronous SRAM, 300 MHz clock, 1.7-1.9V, 165-LBGA.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, QDR II","Memory Size":"36Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Obsolete","Clock Frequency":"300 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C1426","Memory Organization":"4M x 9","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"165-FBGA (15x17)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/24fe006d6404e9087adee005b719f789.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory organization and clock speed of CY7C1426AV18-300BZXC?","answer":"The device is a 36 Mbit QDR II synchronous SRAM organized as 4M × 9 bits, with a 300 MHz clock frequency and a parallel interface. The supply voltage range is 1.7 V to 1.9 V."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1426AV18-300BZXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1426AV18-300BZXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:09:03.718Z","lastPublished":"2026-07-21T02:09:03.718Z","indexable":true}}