{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1414AV18-200BZC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1414AV18-200BZC","canonicalUrl":"https://icboms.com/infineon/CY7C1414AV18-200BZC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1414AV18-200BZC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1414AV18-200BZC, QDR II synchronous SRAM, 36 Mbit, 1M x 36 organization, 200 MHz clock, 1.7–1.9 V, 165-FBGA (15×17) tray, 0°C–70°C.","salesMarkdown":"## 36 Mbit QDR II — 200 MHz synchronous SRAM The CY7C1414AV18-200BZC is a 36 Mbit synchronous SRAM using the QDR II (Quad Data Rate) architecture — it transfers data on both rising and falling edges of the clock on separate read and write ports, effectively quadrupling the data rate relative to a single-port SDR device at the same 200 MHz clock. Organized as 1M x 36, the 36-bit-wide word matches the bus width of many network processors and FPGA soft-core memory controllers — one chip provides a full 36-bit transaction per clock edge without byte-lane gating. Operating from a 1.7 V to 1.9 V core supply, the I/O voltage is typically 1.5 V or 1.8 V HSTL — the parallel interface requires matched on-die termination and reference voltage (Vref) on the PCB to hold signal integrity at the 200 MHz double-data-rate edge rate. ## 165-FBGA package and board integration Housed in a 165-ball FBGA measuring 15 x 17 mm, the package uses a 1.0 mm ball pitch — a standard 4-layer PCB with microvias can fan out the inner rows, though the 36-bit data bus plus address and control signals typically demand at least six signal layers in a high-speed memory channel.","metaTitle":"CY7C1414AV18-200BZC QDR II SRAM 36Mbit 200 MHz","metaDescription":"Infineon CY7C1414AV18-200BZC 36Mbit QDR II SRAM, 200 MHz, 1M x 36, 165-FBGA. Obsolete — sourced to order against RFQ through independent channels.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"title":"CY7C1414AV18-200BZC","Package":"Tray","Technology":"SRAM - Synchronous, QDR II","Memory Size":"36Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Clock Frequency":"200 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C1414","Memory Organization":"1M x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"165-FBGA (15x17)"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/85f29a0dbf8171ed24144f319528c821.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory density and organization of the CY7C1414AV18-200BZC?","answer":"It is a 36 Mbit synchronous SRAM organized as 1M words x 36 bits. The 36-bit-wide data bus suits high-throughput networking and FPGA memory interfaces."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1414AV18-200BZC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1414AV18-200BZC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:08:12.644Z","lastPublished":"2026-07-21T02:08:12.644Z","indexable":true}}