{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1385D-133AXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1385D-133AXI","canonicalUrl":"https://icboms.com/infineon/CY7C1385D-133AXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1385D-133AXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1385D-133AXI synchronous SRAM, 18Mbit (512K x 36), 133 MHz clock, 6.5 ns access, 3.3 V, industrial -40 to 85 °C, 100-TQFP tray.","salesMarkdown":"## 18Mbit synchronous SRAM for high-throughput data paths The Infineon CY7C1385D-133AXI is a 18Mbit synchronous SRAM organized as 512K x 36, clocked at 133 MHz with a 6.5 ns access time. ## What the 133 MHz clock and 6.5 ns access mean for your bus The 133 MHz clock rate and 6.5 ns access time set the read-to-data-valid window for the memory controller. At 133 MHz the cycle time is 7.5 ns, so the 6.5 ns access means data appears on the bus just 1 ns before the next clock edge — the controller must capture within that hold window. The 512K x 36 organization gives a 36-bit wide data bus, useful for processor or DSP interfaces that need a full word per cycle without multiplexing. Infineon lists the CY7C1385D-133AXI as Obsolete. For a BOM already qualified to this footprint and timing, the existing layout and controller settings carry over — no board spin is required if the supply is secured. Supplied in a 100-TQFP (14x20 mm) tray package, surface-mount. The 0.5 mm pitch demands a controlled impedance layout on the data and address lines, especially at 133 MHz.","metaTitle":"Infineon CY7C1385D-133AXI 18Mbit SRAM, 133 MHz, 100-TQFP","metaDescription":"Infineon CY7C1385D-133AXI synchronous SRAM, 18Mbit (512K x 36), 133 MHz, 6.5 ns access, industrial temp, 100-TQFP. Obsolete — sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"title":"CY7C1385D-133AXI","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"6.5 ns","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.14V ~ 3.63V","Base Product Number":"CY7C1385","Memory Organization":"512K x 36","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"100-TQFP (14x20)"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$25.3600","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/aad993d8cfda307cfe98a5076316c9cb.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1385D-133AXI/alternatives.json"},"ai":{"faq":[{"question":"Where can I buy CY7C1385D-133AXI?","answer":"Sourced through independent distribution. Submit an RFQ for current lot status and traceability documentation."},{"question":"What is the memory organization and interface of CY7C1385D-133AXI?","answer":"512K x 36 (18 Mbit) synchronous SRAM with a parallel interface. The 36-bit wide data bus matches processors and DSPs that fetch a full word per clock cycle."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1385D-133AXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1385D-133AXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:07:29.394Z","lastPublished":"2026-07-21T02:07:29.394Z","indexable":true}}