{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1383B-100AC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1383B-100AC","canonicalUrl":"https://icboms.com/infineon/CY7C1383B-100AC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1383B-100AC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1383B-100AC synchronous SRAM, 18Mbit, 1M x 18 organization, 100 MHz clock, 8.5 ns access, 3.135V–3.6V supply, 100-TQFP (14x20 mm), commercial temp 0°C–70°C.","salesMarkdown":"## What this 18Mbit synchronous SRAM does on the bus The CY7C1383B-100AC is a 18Mbit synchronous SRAM organized as 1M x 18, clocked at 100 MHz with a pipelined read/write architecture. The 8.5 ns access time means the first word appears on the bus that many nanoseconds after the address is latched on the rising clock edge — a figure that sets the minimum cycle time for back-to-back reads in a cache or buffer application. The 100-TQFP (14x20 mm) package sits on a 0.5 mm pitch LQFP footprint — the same land pattern used by many synchronous SRAMs in this density class, so a board laid out for a compatible part may accept this device without a spin. Infineon lists the CY7C1383B-100AC as Obsolete. For a BOM line that already uses this order code, the procurement decision is straightforward: source from the open market against a confirmed requirement. ## Timing and supply — the two constraints that govern fit The 100 MHz clock rate and 8.5 ns access time together define the read latency budget. In a pipelined synchronous interface, the controller must account for the pipeline depth (typically two cycles for the first read) plus the access time from the clock edge. A system designed for a 133 MHz or 166 MHz SRAM will not meet timing if this part is substituted without adjusting the controller's wait-state configuration. The supply tolerance is 3.135V to 3.6V — a 3.3V nominal rail with ±5% regulation stays inside this window.","metaTitle":"Infineon CY7C1383B-100AC 18Mbit SRAM, 100 MHz, 8.5 ns","metaDescription":"Infineon CY7C1383B-100AC 18Mbit synchronous SRAM, 1M x 18, 100 MHz clock, 8.5 ns access, 3.135V-3.6V, 100-TQFP.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"title":"CY7C1383B-100AC","Package":"Bag","Technology":"SRAM - Synchronous, SDR","Access Time":"8.5 ns","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Clock Frequency":"100 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1383","Memory Organization":"1M x 18","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/b1f75e15ee47b301575439135dd89180.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the closest pin-compatible alternative to CY7C1383B-100AC?","answer":"The 100-TQFP footprint is shared by many synchronous SRAMs in the 18Mbit density, but a functional replacement requires validating timing, supply, and temperature grade against the specific application."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1383B-100AC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1383B-100AC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:06:52.216Z","lastPublished":"2026-07-21T02:06:52.216Z","indexable":true}}