{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1381D-133BGXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1381D-133BGXC","canonicalUrl":"https://icboms.com/infineon/CY7C1381D-133BGXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1381D-133BGXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1381D-133BGXC synchronous SRAM, 18Mbit, 512K×36 organization, 133 MHz clock, 6.5 ns access, 3.135-3.6 V, 165-LBGA, 0-70 °C.","salesMarkdown":"## 133 MHz synchronous SRAM — 512K×36 in a 165-ball BGA The CY7C1381D-133BGXC: That 36-bit data bus makes it a natural fit for 32-bit processor systems with parity or ECC coverage — the extra four bits serve as byte parity lanes without stealing data bandwidth. The commercial temperature grade (0 °C to 70 °C) limits it to indoor, controlled environments — no cold-start or engine-bay duty. ## Package and board-fit realities Housed in a 165-ball LBGA (13×15 mm body per the supplier device package), the 1.0 mm ball pitch demands a four-layer PCB minimum for fan-out — two-layer boards cannot route the inner rows. The surface-mount footprint is standard for this class of synchronous SRAM; the same ball-out is shared across the CY7C1381D family, so a layout validated for one speed grade carries over to this 133 MHz variant. Supplied in tray packaging — not tape-and-reel. For volume production, factor in tray-to-reel conversion or pick-and-place from tray feeders. Infineon lists the CY7C1381D-133BGXC as obsolete. Quantities are lot-specific and confirmed at RFQ; no stock-holding claim is made here.","metaTitle":"CY7C1381D-133BGXC Infineon 18Mbit SRAM, 133 MHz, 6.5 ns","metaDescription":"CY7C1381D-133BGXC 18Mbit synchronous SRAM, 512K×36, 133 MHz clock, 6.5 ns access, 3.135-3.6 V, 165-LBGA. Obsolete — sourced to order. Request a quote.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"title":"CY7C1381D-133BGXC","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"6.5 ns","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1381","Memory Organization":"512K x 36","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"165-FBGA (13x15)"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/33f0772d818827ec2d8cc0821e3ecd12.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory organization and bus width of CY7C1381D-133BGXC?","answer":"512K words by 36 bits — a 36-bit data bus. The four extra bits over a 32-bit word are typically used for byte-level parity or ECC coverage in systems that need single-bit error detection without a separate parity memory chip."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1381D-133BGXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1381D-133BGXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:06:06.669Z","lastPublished":"2026-07-21T02:06:06.669Z","indexable":true}}