{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1372KV33-167AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1372KV33-167AXC","canonicalUrl":"https://icboms.com/infineon/CY7C1372KV33-167AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1372KV33-167AXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ series synchronous SRAM, CY7C1372KV33-167AXC, 18Mbit (1M x 18), 167 MHz clock, 3.4 ns access, 3.135V–3.6V, 0°C–70°C, 100-TQFP (14x20).","salesMarkdown":"## 18 Mbit synchronous SRAM at 167 MHz — the speed-grade decision The CY7C1372KV33-167AXC: That access time is the window from clock edge to data valid on the bus; at 167 MHz the cycle time is 6 ns, so the 3.4 ns access leaves 2.6 ns of setup and hold margin for the controller. If your FPGA or ASIC memory controller has a tighter input timing budget, this part's speed grade is the one you want. The commercial temperature range (0°C to 70°C) suits networking equipment, test gear, and base stations that live indoors; for extended-temp or automotive requirements this is not the right variant. ## NoBL pipelined architecture — what it means for bus utilisation NoBL (No Bus Latency) means the SRAM can accept a new read or write address on every clock cycle without dead cycles between operations, as long as the pipeline depth is respected. A standard synchronous SRAM inserts a turnaround cycle when switching from read to write; NoBL eliminates it, so the bus stays at 100 % utilisation at the full 167 MHz clock rate. For a cache or packet buffer that alternates read and write access, this lifts throughput without raising the clock. The 18-bit-wide data bus (1M x 18) maps naturally to a 16-bit word plus two parity/ECC bits, or to an 18-bit DSP word. The parallel interface uses the standard synchronous SRAM control set — chip enable, write enable, output enable, byte write selects — so it drops into existing controller designs with minimal glue logic. Housed in a 100-TQFP (14x20 mm) with 0.5 mm pitch — a standard fine-pitch QFP that routes on a 4-layer board without microvias. The exposed pad on the bottom side (if present on this variant) should be stitched to the ground plane with thermal vias; the datasheet's recommended land pattern is the reference for the solder-paste stencil aperture. Surface-mount only; the tray packaging is typical for volume assembly. Confirm the MSL rating on the reel or tray label before opening the sealed bag.","metaTitle":"CY7C1372KV33-167AXC NoBL SRAM, 18Mbit, 167 MHz, 3.4 ns","metaDescription":"Infineon CY7C1372KV33-167AXC NoBL synchronous SRAM, 18Mbit (1M x 18), 167 MHz clock, 3.4 ns access, 3.135V–3.6V, 0°C–70°C, 100-TQFP.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3.4 ns","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"167 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1372","Memory Organization":"1M x 18","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$23.1865","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/8c34dd06a1999ca10efe2a9b1a86dab1.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1372KV33-167AXC/alternatives.json"},"ai":{"faq":[{"question":"What is the closest pin-compatible alternative to the CY7C1372KV33-167AXC?","answer":"The base product number CY7C1372 covers multiple speed grades and temperature ranges within the same package footprint; a slower or faster speed bin (e.g., -133 or -200) in the same 100-TQFP may be pin-compatible, but this must be verified against the respective datasheets."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1372KV33-167AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1372KV33-167AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}