{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1372D-200AXCT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1372D-200AXCT","canonicalUrl":"https://icboms.com/infineon/CY7C1372D-200AXCT","factsUrl":"https://icboms.com/api/mcp/products/CY7C1372D-200AXCT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ synchronous SRAM, CY7C1372D-200AXCT, 18Mbit (1M x 18), 200 MHz clock, 3 ns access time, 3.135V–3.6V supply, 0°C–70°C, 100-TQFP (14x20 mm), Tape & Reel.","salesMarkdown":"## 18 Mbit synchronous SRAM — 200 MHz NoBL pipeline The CY7C1372D-200AXCT is a 18 Mbit synchronous SRAM organised as 1M x 18, clocked at 200 MHz with a 3 ns access time. It belongs to the NoBL™ (No Bus Latency) family, which eliminates the dead cycle between read and write transitions — the bus turns around without an idle clock, so a controller can issue a read immediately after a write at full 200 MHz rate. The parallel interface is a standard synchronous SRAM bus with registered address and data paths. ## Package and board-fit — 100-TQFP, 14x20 mm body The supplier device package is 100-TQFP (14x20) — the footprint matches standard JEDEC MO-136. The tape-and-reel packaging is suited for automated pick-and-place assembly. The part is not recommended for new designs; existing BOM lines must be sourced through independent surplus or broker channels.","metaTitle":"CY7C1372D-200AXCT Infineon NoBL SRAM, 18Mbit, 200 MHz","metaDescription":"CY7C1372D-200AXCT NoBL synchronous SRAM, 18Mbit (1M x 18), 200 MHz clock, 3 ns access, 100-TQFP. Obsolete — sourced to order against RFQ. Request a quote.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tape & Reel (TR)","Technology":"SRAM - Synchronous, SDR","Access Time":"3 ns","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"200 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1372","Memory Organization":"1M x 18","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What is the key advantage of the NoBL architecture in this SRAM?","answer":"NoBL (No Bus Latency) eliminates the idle clock cycle between read and write operations. At 200 MHz, that means the bus can sustain back-to-back read-write transitions without a dead cycle, improving throughput in cache or buffer applications where the controller alternates between reading and writing."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1372D-200AXCT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1372D-200AXCT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:05:16.788Z","lastPublished":"2026-07-21T02:05:16.788Z","indexable":true}}