{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1371KV33-100AXCT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1371KV33-100AXCT","canonicalUrl":"https://icboms.com/infineon/CY7C1371KV33-100AXCT","factsUrl":"https://icboms.com/api/mcp/products/CY7C1371KV33-100AXCT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ SRAM, CY7C1371KV33-100AXCT, 18Mbit (512K x 36), Synchronous SDR, 100 MHz, 8.5 ns access, 100-LQFP, Tape & Reel.","salesMarkdown":"## 18 Mbit synchronous SRAM for high-throughput data paths The CY7C1371KV33-100AXCT is a 18 Mbit synchronous SRAM organized as 512K x 36 bits, clocked at 100 MHz with a 8.5 ns access time from the Infineon NoBL™ (No Bus Latency) series. ## Last-time-buy — sourcing window for production continuity Infineon lists this part in Last Buy status — the manufacturer has announced end-of-life and the final purchasing window is open. For a BOM line that already qualifies this SRAM, the last-time-buy is the procurement trigger: order the forecasted lifetime requirement now, because once the window closes the only channel will be surplus inventory. ## Package and reflow profile for the pick-and-place line The Tape & Reel (TR) packaging means it feeds directly into a pick-and-place machine without a reel change — check the MSL level on the reel label before the bake decision. ## No Bus Latency architecture — why the pipeline matters The NoBL™ (No Bus Latency) pipeline eliminates the dead cycle between read and write operations that conventional synchronous SRAMs require — every clock edge can be a valid data transfer, which raises sustained throughput in a cache line fill or packet buffer without increasing the clock rate. At 100 MHz the part delivers a 10 ns cycle time for any combination of reads and writes, compared to a pipelined SRAM that inserts a turnaround cycle and effectively halves throughput on mixed transactions.","metaTitle":"CY7C1371KV33-100AXCT Infineon SRAM, 18Mbit, 100 MHz","metaDescription":"CY7C1371KV33-100AXCT Infineon NoBL SRAM, 18Mbit (512K x 36), 100 MHz, 8.5 ns access. Last Buy status. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Last Buy","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tape & Reel (TR)","Technology":"SRAM - Synchronous, SDR","Access Time":"8.5 ns","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Last Time Buy","Clock Frequency":"100 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1371","Memory Organization":"512K x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$22.7574","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/859454d91243e0f63fa69b45c819ba95.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1371KV33-100AXCT/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization and clock speed of the CY7C1371KV33-100AXCT?","answer":"It is a 18 Mbit synchronous SRAM organized as 512K x 36 bits, clocked at 100 MHz with a 8.5 ns access time, part of the NoBL™ series that eliminates bus turnaround latency."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1371KV33-100AXCT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1371KV33-100AXCT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:04:49.507Z","lastPublished":"2026-07-21T02:04:49.507Z","indexable":true}}