{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1370KVE33-167AXM","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1370KVE33-167AXM","canonicalUrl":"https://icboms.com/infineon/CY7C1370KVE33-167AXM","factsUrl":"https://icboms.com/api/mcp/products/CY7C1370KVE33-167AXM","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C1370KVE33-167AXM, NoBL series, 18Mbit Synchronous SRAM, 512K x 36 organization, 167 MHz clock, 3.4 ns access time, 3.135V-3.6V supply, 100-LQFP, -55°C to 125°C.","salesMarkdown":"Clocked at 167 MHz with a 3.4 ns access time, it operates from 3.135 V to 3.6 V with a parallel memory interface. ## Military temperature range — what it means for deployment The case temperature spec means the die junction tracks the package surface. ## NoBL architecture — why the bus turnaround matters Standard synchronous SRAMs insert a dead cycle when switching from read to write (or write to read), wasting a clock edge. The NoBL pipeline eliminates that gap, allowing back-to-back transactions at full 167 MHz throughput. For a 512K x 36 memory bus feeding a DSP or FPGA, that means no pipeline stalls on mixed read/write sequences—critical in radar signal processing or real-time control loops where every cycle counts. The trade-off: NoBL parts use a slightly different control logic (ADV/LD rather than simple chip-enable timing), so verify the controller interface before dropping it into a legacy socket designed for a pipelined SRAM without NoBL. Listed as Active on the manufacturer status, but the eol_hot lifecycle stage flags this part as approaching end-of-life.","metaTitle":"Cypress CY7C1370KVE33-167AXM 18Mbit NoBL SRAM, 167 MHz","metaDescription":"Cypress CY7C1370KVE33-167AXM 18Mbit synchronous SRAM with NoBL architecture, 3.4 ns access time, 167 MHz clock, -55°C to 125°C. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3.4 ns","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"167 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1370","Memory Organization":"512K x 36","Operating Temperature":"-55°C ~ 125°C (TC)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$30.8614","priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1370KVE33-167AXM/alternatives.json"},"ai":{"faq":[{"question":"What does the NoBL series mean on this SRAM?","answer":"NoBL stands for No Bus Latency—the architecture eliminates dead cycles between read and write operations, allowing back-to-back transactions at the full 167 MHz clock rate without pipeline stalls."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1370KVE33-167AXM","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1370KVE33-167AXM when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}