{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1370D-200AXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1370D-200AXI","canonicalUrl":"https://icboms.com/infineon/CY7C1370D-200AXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1370D-200AXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1370D-200AXI, NoBL™ series, 18Mbit Synchronous SRAM, 200 MHz clock frequency, 3 ns access time, 512K x 36 organization, Parallel interface, 3.135V~3.6V supply, -40°C~85°C, 100-LQFP, Surface Mount, Tray.","salesMarkdown":"## High-speed synchronous SRAM with NoBL architecture ## 200 MHz clock and 3 ns access — what they mean for timing closure The 200 MHz clock frequency sets the maximum operating rate for the memory interface. At this speed, the 3 ns access time defines the window from clock edge to valid data on the bus. For a system architect, this means the FPGA or ASIC controller must budget for a 3 ns tCO plus board trace delay and still meet setup time on the receiving end. The 512K x 36 organization provides 18 Mbit of storage with a 36-bit wide data path, suitable for 32-bit plus parity or ECC applications. The 100-TQFP (14x20 mm) package is a standard fine-pitch surface-mount footprint with 0.5 mm lead pitch. Infineon has classified the CY7C1370D-200AXI as Obsolete. There is no pin-compatible direct replacement from Infineon's current SRAM portfolio; any substitution would require a board respin and revalidation of the memory controller timing.","metaTitle":"Infineon CY7C1370D-200AXI 18Mbit NoBL SRAM, 200 MHz","metaDescription":"Infineon CY7C1370D-200AXI 18Mbit synchronous SRAM, 200 MHz clock, 3 ns access, 512K x 36, 100-TQFP, -40°C to 85°C.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3 ns","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"200 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1370","Memory Organization":"512K x 36","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What is the replacement for CY7C1370D-200AXI?","answer":"Infineon has not published a direct pin-compatible successor for the CY7C1370D-200AXI. Any replacement would require a board-level redesign and memory controller retiming. For existing designs, the only option is sourcing the original part through the surplus channel."},{"question":"What is the access time of CY7C1370D-200AXI?","answer":"The access time is 3 ns, measured from the active clock edge. At a 200 MHz clock rate, this gives a 5 ns cycle period, so the 3 ns access leaves 2 ns for address-to-clock setup and board delay before the next cycle."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1370D-200AXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1370D-200AXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}