{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1370D-167AXIT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1370D-167AXIT","canonicalUrl":"https://icboms.com/infineon/CY7C1370D-167AXIT","factsUrl":"https://icboms.com/api/mcp/products/CY7C1370D-167AXIT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ series, CY7C1370D-167AXIT synchronous SRAM, 18Mbit, 512K x 36, 167 MHz, 3.4 ns access, 3.135V-3.6V, industrial -40°C to 85°C, 100-TQFP, Tape & Reel.","salesMarkdown":"## NoBL architecture and bus timing The CY7C1370D-167AXIT: The NoBL (No Bus Latency) pipeline eliminates the turnaround cycle between read and write on the same port — the next access starts on the clock edge following the address, not after a wait state. At 167 MHz this saves one clock per transaction direction change, which matters when the memory is shared between a processor and a DMA engine. The parallel interface uses a common address and data bus, so the controller must match the timing to the SRAM's spec sheet limits. Infineon lists the CY7C1370D-167AXIT as Obsolete.","metaTitle":"CY7C1370D-167AXIT Infineon 18Mbit SRAM, 167 MHz, 100-TQFP","metaDescription":"CY7C1370D-167AXIT 18Mbit synchronous SRAM, 167 MHz clock, 3.4 ns access, 512K x 36, industrial temp. Obsolete — sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tape & Reel (TR)","Technology":"SRAM - Synchronous, SDR","Access Time":"3.4 ns","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"167 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1370","Memory Organization":"512K x 36","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$35.8000","priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1370D-167AXIT/alternatives.json"},"ai":{"faq":[{"question":"Where can I source the CY7C1370D-167AXIT?","answer":"The CY7C1370D-167AXIT is obsolete per Infineon. It is available through independent distribution — submit an RFQ for current availability and pricing. No stock-holding claim is made; each lot is confirmed at quote time."},{"question":"What is the memory organization of the CY7C1370D-167AXIT?","answer":"The SRAM is organized as 512K words by 36 bits (18 Mbit total). The 36-bit word width matches a 32-bit data bus plus four parity or ECC bits without needing a second device."},{"question":"Is the CY7C1370D-167AXIT suitable for new designs?","answer":"No — the part is obsolete. New designs should evaluate current-generation synchronous SRAMs from Infineon or alternate suppliers with compatible pinouts and timing."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1370D-167AXIT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1370D-167AXIT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:04:35.671Z","lastPublished":"2026-07-21T02:04:35.671Z","indexable":true}}