{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C136E-25JXIT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C136E-25JXIT","canonicalUrl":"https://icboms.com/infineon/CY7C136E-25JXIT","factsUrl":"https://icboms.com/api/mcp/products/CY7C136E-25JXIT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C136E-25JXIT, 16Kbit dual-port asynchronous SRAM, 2K x 8 organization, 25 ns access time, 4.5-5.5 V supply, -40 to 85 °C, 52-PLCC (J-Lead), Tape & Reel.","salesMarkdown":"## Dual-port arbitration and bus timing The CY7C136E-25JXIT: In a dual-port SRAM, both ports can read or write any memory location simultaneously — the 25 ns spec is the time from address valid to data valid on the bus, and it defines the minimum cycle time for back-to-back accesses. For a system clocked at 40 MHz (25 ns period), the access time consumes the entire cycle, so wait states are needed if the bus master runs faster than the memory's native speed. ## Industrial temperature and 5 V logic domain The 52-PLCC (J-Lead) package is a through-hole-reflow-friendly footprint; the leads are visible for inspection and rework, unlike a BGA that requires X-ray. The supplier device package is 52-PLCC (19.13x19.13 mm). Infineon lists the CY7C136E-25JXIT as Obsolete. For a BOM that requires this exact dual-port SRAM in the 52-PLCC footprint, the procurement path is a last-time-buy or surplus sourcing — there is no pin-compatible drop-in replacement from Infineon's current active portfolio.","metaTitle":"Infineon CY7C136E-25JXIT 16Kbit Dual-Port SRAM, 25 ns","metaDescription":"Obsolete Infineon CY7C136E-25JXIT 16Kbit dual-port asynchronous SRAM, 2Kx8, 25 ns access, 4.5-5.5 V, -40 to 85 °C, 52-PLCC. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tape & Reel (TR)","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"25 ns","Memory Size":"16Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"52-LCC (J-Lead)","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C136","Memory Organization":"2K x 8","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"52-PLCC (19.13x19.13)","Write Cycle Time - Word, Page":"25ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/19afd1f6d8fd2391099b1102dec838b2.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C136E-25JXIT/alternatives.json"},"ai":{"faq":[{"question":"Is the CY7C136E-25JXIT discontinued?","answer":"Yes, Infineon lists the CY7C136E-25JXIT as Obsolete. The part is sourced through independent surplus channels; availability is confirmed per RFQ."},{"question":"What is the access time of the CY7C136E-25JXIT?","answer":"The access time is 25 ns. This is the time from address valid to data valid on the bus, and it sets the minimum cycle time for back-to-back dual-port accesses."},{"question":"What package does the CY7C136E-25JXIT use?","answer":"The J-Lead footprint is rework-friendly and does not require X-ray inspection."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C136E-25JXIT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C136E-25JXIT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:04:00.464Z","lastPublished":"2026-07-21T02:04:00.464Z","indexable":true}}