{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1366C-166AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1366C-166AXC","canonicalUrl":"https://icboms.com/infineon/CY7C1366C-166AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1366C-166AXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1366C-166AXC synchronous SDR SRAM, 9Mbit (256K x 36), 166 MHz clock, 3.5 ns access, 3.135-3.6V, 100-TQFP (14x20), tray.","salesMarkdown":"## 256K x 36 synchronous SRAM — 166 MHz pipeline The CY7C1366C-166AXC is a 9Mbit synchronous SDR (single-data-rate) SRAM organised as 256K words by 36 bits. The 166 MHz clock rate yields a 3.5 ns access time from clock rise, which sets the read-to-data-valid window for the downstream logic — the pipeline depth means the first read incurs the full latency, but subsequent back-to-back reads issue one per clock cycle. The 36-bit-wide data bus maps naturally to 32-bit processor buses with four parity/ECC bits, or to a 36-bit DSP word. The parallel interface eliminates serialisation overhead, so the throughput ceiling is the clock rate times the bus width: 166 MHz × 36 bits = 5.976 Gbit/s raw bandwidth. ## Supply rails and temperature grade For extended-temperature designs this part is not rated; the industrial-grade sibling in the same family would be the correct call. ## Package and footprint Supplied in a 100-lead LQFP (EIAJ standard), the supplier device package is the 100-TQFP with a 14×20 mm body. The 0.5 mm pitch requires a four-layer PCB for reliable fan-out of the inner rows — two-layer boards will struggle to route the 36 data lines plus address and control without via congestion. Tray packaging is the standard delivery format for this order code. ## Last Buy — planning the BOM transition Infineon has placed the CY7C1366C-166AXC into Last Buy status. This means the manufacturer will accept final orders for a defined window, after which the part is discontinued with no further production. Any new design should avoid this order code; existing production that depends on it should secure last-time-buy quantities or qualify a replacement before the cutoff. The closest functional replacement would be a pin-compatible synchronous SRAM from the same Cypress/Infineon family with the same 100-TQFP footprint — confirm the exact ordering code against the BOM position before committing.","metaTitle":"Infineon CY7C1366C-166AXC 9Mbit SRAM, 166 MHz, 100-TQFP","metaDescription":"Infineon CY7C1366C-166AXC synchronous SDR SRAM, 256K x 36, 166 MHz clock, 3.5 ns access, 3.135-3.6V, 100-TQFP. Last Buy lifecycle — sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Last Buy","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3.5 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Last Time Buy","Clock Frequency":"166 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1366","Memory Organization":"256K x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$13.8800","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/6e803a233592551a93e12554c6ddd018.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1366C-166AXC/alternatives.json"},"ai":{"faq":[{"question":"What does the 3.5 ns access time mean for my timing budget?","answer":"The 3.5 ns is the clock-to-data-valid delay at 166 MHz. In a typical pipeline read, the address is registered on the first clock edge and data appears 3.5 ns after the second clock edge. The downstream FPGA or ASIC must capture the data within the remaining portion of the clock period — at 166 MHz (6.02 ns cycle) that leaves about 2.5 ns for board trace delay, input capacitance settling, and setup time. Budget this into your static timing analysis."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1366C-166AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1366C-166AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:03:50.101Z","lastPublished":"2026-07-21T02:03:50.101Z","indexable":true}}