{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1363C-133AJXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1363C-133AJXC","canonicalUrl":"https://icboms.com/infineon/CY7C1363C-133AJXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1363C-133AJXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1363C-133AJXC synchronous SRAM, 9Mbit, 512K x 18 organization, 133 MHz clock, 6.5 ns access, 100-TQFP, tray.","salesMarkdown":"## What the 133 MHz clock and 6.5 ns access time mean for your bus The CY7C1363C-133AJXC is a 9 Mbit synchronous SRAM organized as 512K x 18 bits. The 133 MHz clock frequency means the memory can deliver one 18-bit word per clock cycle in burst mode, which is the standard interface for high-speed cache or buffer applications in networking and telecom equipment. The 6.5 ns access time is the time from the address being latched to data appearing on the outputs; at 133 MHz the clock period is about 7.5 ns, so the access time leaves roughly 1 ns of setup margin for the downstream logic — tight, but within spec for a properly terminated bus. ## Supply voltage and interface The parallel memory interface is a 18-bit data bus plus address and control signals; the 512K x 18 organization means 19 address lines. The base product number is CY7C1363, which helps when searching for related variants or errata documents. Infineon lists this part as Obsolete. Availability is lot-specific and confirmed at RFQ; pricing is market-driven and quoted per request.","metaTitle":"CY7C1363C-133AJXC 9Mbit SRAM, 133 MHz, 100-TQFP","metaDescription":"CY7C1363C-133AJXC 9Mbit synchronous SRAM, 133 MHz clock, 6.5 ns access, 100-TQFP. Obsolete — sourced to order. Request a quote.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"6.5 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1363","Memory Organization":"512K x 18","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$11.3600","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/25ee5b83ca7d8f09e984f37e39e01b05.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1363C-133AJXC/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization of CY7C1363C-133AJXC?","answer":"The CY7C1363C-133AJXC is organized as 512K words by 18 bits, giving a total memory size of 9 Mbit. The 18-bit word width is typical for systems that need parity or ECC alongside 16-bit data."},{"question":"What package does CY7C1363C-133AJXC use?","answer":"It comes in a 100-lead LQFP package, specifically the supplier device package 100-TQFP with a 14x20 mm body. It is supplied in trays."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1363C-133AJXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1363C-133AJXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:03:16.200Z","lastPublished":"2026-07-21T02:03:16.200Z","indexable":true}}