{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1361C-133AXIT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1361C-133AXIT","canonicalUrl":"https://icboms.com/infineon/CY7C1361C-133AXIT","factsUrl":"https://icboms.com/api/mcp/products/CY7C1361C-133AXIT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1361C-133AXIT synchronous SRAM, 9Mbit, 256K x 36, 133 MHz clock, 6.5 ns access, 3.135V-3.6V, -40°C to 85°C, 100-TQFP, Tape & Reel.","salesMarkdown":"## 133 MHz synchronous pipeline — what the clock and access time mean for your bus The CY7C1361C-133AXIT: The 36-bit word width is the defining fit criterion — it matches processors and ASICs with a 36-bit data bus (common in networking and telecom line cards) where a narrower 32-bit part would leave two byte lanes unconnected or require a second chip. The 133 MHz clock means the part can sustain a pipelined read or write every cycle once the initial latency is absorbed, which keeps the bus saturated without wait states. The supply range is 3.135 V to 3.6 V, which is a tight 3.3 V nominal with ±7 % tolerance. ## Package and mounting — 100-TQFP layout notes The part is supplied in a 100-LQFP package (also designated 100-TQFP, 14 mm x 20 mm body). The 0.5 mm pitch demands a PCB with fine-line etch capability — a 4-layer board with buried vias under the body is typical for fan-out. ## Active lifecycle — no design-in risk Infineon lists the CY7C1361C-133AXIT as Active. The base product number CY7C1361 covers the family; speed and temperature variants within it share the same pinout and footprint, giving a drop-in upgrade path if a faster or wider-temperature version is needed later. The Tape & Reel (TR) packaging is the standard delivery format for automated pick-and-place assembly; reel quantities are confirmed per RFQ.","metaTitle":"Infineon CY7C1361C-133AXIT 9Mbit Sync SRAM, 133 MHz","metaDescription":"Active 9Mbit synchronous SRAM, 256K x 36 organization, 133 MHz clock, 6.5 ns access, -40°C to 85°C. 100-TQFP. Sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tape & Reel (TR)","Technology":"SRAM - Synchronous, SDR","Access Time":"6.5 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1361","Memory Organization":"256K x 36","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$13.0725","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/25ee5b83ca7d8f09e984f37e39e01b05.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1361C-133AXIT/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization and why does the 36-bit width matter?","answer":"The part is organized as 256K words by 36 bits. The 36-bit width is common in networking and telecom equipment where the data bus is 36 bits wide (e.g., for parity or ECC alongside 32 data bits). A standard 32-bit SRAM would leave four data lines unconnected or require a second device to cover the full bus."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1361C-133AXIT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1361C-133AXIT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}