{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1361C-133AJXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1361C-133AJXC","canonicalUrl":"https://icboms.com/infineon/CY7C1361C-133AJXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1361C-133AJXC","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C1361C-133AJXC, 9Mbit Synchronous SDR SRAM, 256K x 36 organization, 133 MHz clock, 6.5 ns access time, Parallel interface, 3.135V–3.6V supply, 0°C~70°C, 100-TQFP (14x20).","salesMarkdown":"## 9 Mbit synchronous SRAM with a 36-bit datapath The Cypress CY7C1361C-133AJXC is a 9 Mbit synchronous pipelined SRAM organized as 256K words by 36 bits. It clocks at 133 MHz with a 6.5 ns access time from clock rising edge, which means the read data is valid on the bus within one clock cycle at that frequency. The part runs from a 3.135V to 3.6V supply, so it sits comfortably on a nominal 3.3V rail with margin for regulator droop. The parallel interface uses standard synchronous SRAM control signals — address, data, chip enable, output enable, and byte write enables for the four byte lanes. For existing BOM lines that need this exact part, supply runs through independent distribution — surplus, new-old-stock, and broker inventory. The 'C' revision brought a faster clock speed and tighter access time; the 'B' runs at lower frequency. Verify the timing parameters against your bus budget before substituting — the 'B' may not meet a 133 MHz requirement. ## 133 MHz clock and 6.5 ns access — reading the timing budget The 133 MHz clock rate corresponds to a 7.5 ns cycle period. The 6.5 ns access time (clock to data valid) leaves 1.0 ns of setup margin at the receiver in a zero-delay ideal case. In practice, board trace delay, clock skew, and output loading eat into that margin. This part is designed for systems with tight timing closure — you will need controlled-impedance traces and matched clock distribution to hold the bus at 133 MHz. The pipelined architecture adds one cycle of latency on reads, which the memory controller must account for in its wait-state logic. ## 100-pin TQFP — footprint and reflow notes The package is a 100-lead TQFP with 0.5 mm pitch, body size 14 mm x 20 mm. The part is surface-mount only. No MSL rating is in the record, but Cypress typically rated these synchronous SRAMs at MSL 3; verify the moisture-sensitive label on the actual reel or tray before reflow. If the pouch seal is compromised, bake at 125°C for 48 hours to avoid popcorning.","metaTitle":"Cypress CY7C1361C-133AJXC 9Mbit SDR SRAM, 133 MHz, 6.5 ns","metaDescription":"Cypress CY7C1361C-133AJXC 9Mbit synchronous SRAM, 256K x 36, 133 MHz clock, 6.5 ns access. 100-TQFP, 3.3V supply, commercial temp.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"6.5 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1361","Memory Organization":"256K x 36","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$10.2100","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/25ee5b83ca7d8f09e984f37e39e01b05.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1361C-133AJXC/alternatives.json"},"ai":{"faq":[{"question":"What is the replacement for CY7C1361C-133AJXC?","answer":"The CY7C1361B shares the same 100-pin QFP footprint and 256K x 36 organization, but runs at a lower clock speed. Verify timing compatibility before substituting."},{"question":"Is CY7C1361C-133AJXC compatible with a 3.3V supply?","answer":"Yes. The supply range is 3.135V to 3.6V, so a nominal 3.3V rail is within spec with margin for ripple and droop."},{"question":"What is the difference between CY7C1361C and CY7C1361B?","answer":"The 'C' revision runs at 133 MHz with a 6.5 ns access time. The 'B' revision is a slower speed grade — check its datasheet for the exact clock and access time ratings. Both share the same package and memory organization."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1361C-133AJXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1361C-133AJXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}