{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1360C-166AJXCT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1360C-166AJXCT","canonicalUrl":"https://icboms.com/infineon/CY7C1360C-166AJXCT","factsUrl":"https://icboms.com/api/mcp/products/CY7C1360C-166AJXCT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1360C-166AJXCT synchronous SRAM, 9Mbit (256K x 36), 166 MHz clock, 3.5 ns access time, 100-LQFP, Tape & Reel.","salesMarkdown":"## 9 Mbit synchronous SRAM for high-throughput data buffering The Infineon CY7C1360C-166AJXCT is a 9 Mbit synchronous SRAM organised as 256K x 36 bits, clocked at 166 MHz with a 3.5 ns access time. As an SDR (Single Data Rate) synchronous SRAM, it latches addresses and data on the rising clock edge, making it a fit for networking buffers, cache memory, and DSP pipelines where deterministic read/write timing matters. ## 166 MHz clock and 3.5 ns access — what they mean for the bus The 166 MHz clock frequency gives a 6 ns cycle time. The 3.5 ns access time means data appears at the outputs within 3.5 ns of the clock edge — this leaves 2.5 ns of the cycle for the controller to capture the data, including board trace delay and input setup time. In a 36-bit-wide bus, each read or write cycle moves 36 bits per clock. At 166 MHz, the peak bandwidth is roughly 747 MB/s (166 MHz × 36 bits ÷ 8). The 256K depth gives 262,144 unique address locations per chip. No official successor or pin-compatible replacement is recorded on the lifecycle notice. Quantities are lot-specific and confirmed at RFQ. The 100-LQFP package (14x20 mm body, 0.5 mm pitch) and Tape & Reel packaging match the original production format. Operating temperature is commercial grade (0°C to 70°C).","metaTitle":"Infineon CY7C1360C-166AJXCT 9Mbit SRAM, 166 MHz, 3.5 ns","metaDescription":"Obsolete Infineon CY7C1360C-166AJXCT synchronous SRAM, 9Mbit (256K x 36), 166 MHz clock, 3.5 ns access.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tape & Reel (TR)","Technology":"SRAM - Synchronous, SDR","Access Time":"3.5 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"166 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1360","Memory Organization":"256K x 36","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$12.7900","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/dc1db48580481110015f8cb42078f95e.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1360C-166AJXCT/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organisation and interface of this SRAM?","answer":"It is organised as 256K x 36 bits (9 Mbit total) with a parallel memory interface. The 36-bit word width suits processors or FPGAs with a 36-bit data bus."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1360C-166AJXCT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1360C-166AJXCT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:01:51.331Z","lastPublished":"2026-07-21T02:01:51.331Z","indexable":true}}