{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1357C-133AXCT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1357C-133AXCT","canonicalUrl":"https://icboms.com/infineon/CY7C1357C-133AXCT","factsUrl":"https://icboms.com/api/mcp/products/CY7C1357C-133AXCT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ synchronous SRAM, CY7C1357C-133AXCT, 9Mbit (512K x 18), 133 MHz clock, 6.5 ns access time, 3.135V-3.6V, 100-TQFP (14x20), Tape & Reel.","salesMarkdown":"## 133 MHz synchronous SRAM for pipeline-bound designs The CY7C1357C-133AXCT is a 9Mbit synchronous SRAM organized 512K x 18, clocked at 133 MHz with a 6.5 ns access time. It belongs to Infineon's NoBL™ (No Bus Latency) family, which eliminates the dead bus cycle between reads and writes — the data bus stays active every clock edge, so a write can follow a read without an idle cycle. ## Where the 133 MHz clock and 512K x 18 organization matter The 133 MHz clock rate and 18-bit data width target networking equipment — switch buffers, router forwarding tables, and line-card packet memory — where the bus must sustain back-to-back transactions without wait states. The 512K depth per chip provides 9 Mbit of look-up table or temporary storage in a single package. The 100-TQFP (14x20 mm) footprint is a standard fine-pitch quad flat pack; the 0.5 mm pitch requires controlled impedance routing on the data lines if the board runs the full 133 MHz clock edge rate.","metaTitle":"Infineon CY7C1357C-133AXCT 9Mbit SRAM, 133 MHz, 100-TQFP","metaDescription":"Infineon CY7C1357C-133AXCT NoBL synchronous SRAM, 512K x 18, 133 MHz clock, 6.5 ns access. Active production, 100-TQFP. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tape & Reel (TR)","Technology":"SRAM - Synchronous, SDR","Access Time":"6.5 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1357","Memory Organization":"512K x 18","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$13.1950","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/2777ab46352ffe7e03a8e61ba0b8eaa5.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1357C-133AXCT/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization and clock speed of CY7C1357C-133AXCT?","answer":"The CY7C1357C-133AXCT is organized 512K x 18 (9Mbit total) and runs at a 133 MHz clock with a 6.5 ns access time."},{"question":"What is the NoBL architecture on this SRAM?","answer":"NoBL (No Bus Latency) means the data bus eliminates the dead cycle between read and write operations — the bus remains active every clock edge, so a write can follow a read without an idle cycle."},{"question":"What package does CY7C1357C-133AXCT come in?","answer":"It is shipped in Tape & Reel (TR) format."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1357C-133AXCT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1357C-133AXCT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}