{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1357C-100BZC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1357C-100BZC","canonicalUrl":"https://icboms.com/infineon/CY7C1357C-100BZC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1357C-100BZC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ CY7C1357C-100BZC synchronous SRAM, 9Mbit (512K x 18), 100 MHz clock frequency, 7.5 ns access time, parallel interface, 3.135V–3.6V supply, 0°C–70°C, 165-FBGA (13x15), tray.","salesMarkdown":"## 100 MHz synchronous SRAM with 7.5 ns access The Infineon CY7C1357C-100BZC is a 9Mbit synchronous SRAM organized as 512K x 18, clocked at 100 MHz with a 7.5 ns access time. This places it in the NoBL™ (No Bus Latency) family, where the pipelined architecture eliminates the dead cycle between read and write transitions on the same address — the bus stays full on back-to-back operations. The 7.5 ns access time at 100 MHz means the first data word appears on the bus within one clock cycle after the address is registered. For a system architect sizing the memory subsystem, this sets the read-to-data latency floor: the controller must budget one clock for address-to-data, then one word per clock thereafter in burst mode. ## Supply rails and temperature grade The supply range is 3.135 V to 3.6 V, a narrow 3.3 V nominal band. The 165-FBGA package (13x15 mm) is a fine-pitch BGA. The 0.80 mm ball pitch demands a 4-layer PCB minimum for fan-out; the inner rows require via-in-pad or microvia escape routing. ## Active lifecycle and supply posture No stock-holding claim is made; the part is sourced per the buyer's volume and delivery schedule.","metaTitle":"Infineon CY7C1357C-100BZC NoBL SRAM, 9Mbit, 100 MHz","metaDescription":"Infineon CY7C1357C-100BZC synchronous SRAM, 9Mbit (512K x 18), 100 MHz clock, 7.5 ns access time, 165-FBGA. Active production, quoted to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"7.5 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Active","Clock Frequency":"100 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1357","Memory Organization":"512K x 18","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"165-FBGA (13x15)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$4.5600","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/2777ab46352ffe7e03a8e61ba0b8eaa5.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1357C-100BZC/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization of CY7C1357C-100BZC?","answer":"The device is organized as 512K words by 18 bits, for a total of 9 Mbit. The 18-bit data bus supports byte parity (two 9-bit bytes) or a 16-bit data path with two parity bits, common in networking and telecom line-card applications."},{"question":"What package does CY7C1357C-100BZC use?","answer":"The fine-pitch BGA requires a 4-layer PCB for fan-out and careful routing of the inner ball rows."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1357C-100BZC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1357C-100BZC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}